參數(shù)資料
型號: PIC18F248-I/SO
廠商: Microchip Technology
文件頁數(shù): 92/116頁
文件大?。?/td> 0K
描述: IC MCU FLASH 8KX16 CAN 28SOIC
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 27
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 40MHz
連通性: CAN,I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 22
程序存儲器容量: 16KB(8K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 5x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 管件
配用: XLT28SO-1-ND - SOCKET TRANSITION 28SOIC 300MIL
其它名稱: PIC18F248I/SO
2006 Microchip Technology Inc.
DS41159E-page 75
PIC18FXX8
7.0
8 x 8 HARDWARE MULTIPLIER
7.1
Introduction
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18FXX8 devices. By making the multiply a
hardware operation, it completes in a single instruction
cycle. This is an unsigned multiply that gives a 16-bit
result. The result is stored in the 16-bit product register
pair (PRODH:PRODL). The multiplier does not affect
any flags in the ALUSTA register.
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
Higher computational throughput
Reduces code size requirements for multiply
algorithms
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
Table 7-1 shows a performance comparison between
Enhanced devices using the single-cycle hardware
multiply and performing the same function without the
hardware multiply.
7.2
Operation
Example 7-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
Example 7-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s Most Significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 7-1:
8 x 8 UNSIGNED
MULTIPLY ROUTINE
EXAMPLE 7-2:
8 x 8 SIGNED MULTIPLY
ROUTINE
TABLE 7-1:
PERFORMANCE COMPARISON
MOVF
ARG1, W
;
MULWF
ARG2
; ARG1 * ARG2 ->
;
PRODH:PRODL
MOVF
ARG1, W
MULWF
ARG2
; ARG1 * ARG2 ->
; PRODH:PRODL
BTFSC
ARG2, SB
; Test Sign Bit
SUBWF
PRODH
; PRODH = PRODH
;
- ARG1
MOVF
ARG2, W
BTFSC
ARG1, SB
; Test Sign Bit
SUBWF
PRODH
; PRODH = PRODH
;
- ARG2
Routine
Multiply Method
Program
Memory
(Words)
Cycles
(Max)
Time
@ 40 MHz
@ 10 MHz
@ 4 MHz
8 x 8 unsigned
Without hardware multiply
13
69
6.9
μs
27.6
μs
69
μs
Hardware multiply
1
100 ns
400 ns
1
μs
8 x 8 signed
Without hardware multiply
33
91
9.1
μs
36.4
μs
91
μs
Hardware multiply
6
600 ns
2.4
μs6 μs
16 x 16 unsigned
Without hardware multiply
21
242
24.2
μs
96.8
μs
242
μs
Hardware multiply
24
2.4
μs9.6 μs
24
μs
16 x 16 signed
Without hardware multiply
52
254
25.4
μs102.6 μs
254
μs
Hardware multiply
36
3.6
μs
14.4
μs
36
μs
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