參數(shù)資料
型號： PIC18F248-I/SO
廠商： Microchip Technology
文件頁數(shù)： 34/116頁
文件大?。?/td> 0K
描述： IC MCU FLASH 8KX16 CAN 28SOIC
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝： 27
系列： PIC® 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 40MHz
連通性： CAN，I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 22
程序存儲器容量： 16KB（8K x 16）
程序存儲器類型： 閃存
EEPROM 大小： 256 x 8
RAM 容量： 768 x 8
電壓 - 電源 (Vcc/Vdd)： 4.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 5x10b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
包裝： 管件
配用： XLT28SO-1-ND - SOCKET TRANSITION 28SOIC 300MIL
其它名稱： PIC18F248I/SO
2009 Microchip Technology Inc.
Preliminary
DS41364D-page 285
PIC16F193X/LF193X
REGISTER 23-2:
SSPCON1: SSP CONTROL REGISTER 1
R/C/HS-0/0
R/W-0/0
WCOL
SSPOV
SSPEN
CKP
SSPM<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HS = Bit is set by hardware
C = User cleared
bit 7
WCOL:
Write Collision Detect bit
Master mode:
1
= A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started
0
= No collision
Slave mode:
1
= The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software)
0
= No collision
bit 6
SSPOV:
Receive Overflow Indicator bit(1)
In SPI mode:
1
= A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost.
Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPBUF, even if only transmitting data, to avoid
setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the
SSPBUF register (must be cleared in software).
0
= No overflow
In I2C mode:
1
= A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode
(must be cleared in software).
0
= No overflow
bit 5
SSPEN:
Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output
In SPI mode:
1
= Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2)
0
= Disables serial port and configures these pins as I/O port pins
In I2C mode:
1
= Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3)
0
= Disables serial port and configures these pins as I/O port pins
bit 4
CKP:
Clock Polarity Select bit
In SPI mode:
1
= Idle state for clock is a high level
0
= Idle state for clock is a low level
In I2C Slave mode:
SCL release control
1
= Enable clock
0
= Holds clock low (clock stretch). (Used to ensure data setup time.)
In I2C Master mode:
Unused in this mode
bit 3-0
SSPM<3:0>:
Synchronous Serial Port Mode Select bits
0000
= SPI Master mode, clock = FOSC/4
0001
= SPI Master mode, clock = FOSC/16
0010
= SPI Master mode, clock = FOSC/64
0011
= SPI Master mode, clock = TMR2 output/2
0100
= SPI Slave mode, clock = SCK pin, SS pin control enabled
0101
= SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0110
= I2C Slave mode, 7-bit address
0111
= I2C Slave mode, 10-bit address
1000
= I2C Master mode, clock = FOSC / (4 * (SSPADD+1))(4)
1001
= Reserved
1010
= SPI Master mode, clock = FOSC/(4 * (SSPADD+1))
1011
= I2C firmware controlled Master mode (Slave idle)
1100
= Reserved
1101
= Reserved
1110
= I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1111
= I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
Note
1:
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register.
2:
When enabled, these pins must be properly configured as input or output.
3:
When enabled, the SDA and SCL pins must be configured as inputs.
4:
SSPADD values of 0, 1 or 2 are not supported for I2C Mode.
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