PIC18FXX2
DS39564A-page 308
Advance Information
2001 Microchip Technology Inc.
Repeat START Condition
.........................................152
Slave Synchronization
..............................................129
Slow Rise Time (MCLR Tied to V
DD
)
.........................33
SPI Mode Timing (Master Mode) SPI Mode
Master Mode Timing Diagram
..........................128
SPI Mode Timing (Slave Mode with CKE = 0)
.........130
SPI Mode Timing (Slave Mode with CKE = 1)
.........130
STOP Condition Receive or Transmit
......................156
Time-out Sequence on POR w/PLL Enabled
(MCLR Tied to V
DD
)
...........................................33
Time-out Sequence on Power-up
(MCLR Not Tied to V
DD
)
Case 1
................................................................32
Case 2
................................................................32
Time-out Sequence on Power-up
(MCLR Tied to V
DD
)
...........................................32
Timing for Transition Between Timer1 and
OSC1 (HS with PLL)
..........................................23
Transition Between Timer1 and
OSC1 (HS, XT, LP)
............................................22
Transition Between Timer1 and
OSC1 (RC, EC)
..................................................23
Transition from OSC1 to Timer1 Oscillator
................22
USART Asynchronous Master Transmission
...........170
USART Asynchronous Reception
............................172
USART Synchronous Reception
..............................175
USART Synchronous Transmission
.........................174
Wake-up from SLEEP via Interrupt
..........................204
Timing Diagrams and Specifications
................................268
A/D Conversion
........................................................285
A/D Conversion Requirements
.................................285
Brown-out Reset (BOR)
...........................................271
Capture/Compare/PWM (CCP)
................................273
Capture/Compare/PWM Requirements
...................273
CLKOUT and I/O
......................................................269
CLKOUT and I/O Requirements
..............................270
Example SPI Master Mode (CKE = 0)
.....................275
Example SPI Master Mode (CKE = 1)
.....................276
Example SPI Mode Requirements
(Master Mode, CKE = 0)
..................................275
Example SPI Mode Requirements
(Master Mode, CKE = 1)
..................................276
Example SPI Mode Requirements
(Slave Mode CKE = 0)
.....................................277
Example SPI Slave Mode (CKE = 0)
.......................277
Example SPI Slave Mode (CKE = 1)
.......................278
Example SPI Slave Mode Requirements
(CKE = 1)
.........................................................278
External Clock (All Modes except PLL)
....................268
External Clock Requirements
...................................268
I
2
C Bus Data
............................................................279
I
2
C Bus Data Requirements (Slave Mode)
..............280
I
2
C Bus START/STOP Bits
......................................279
Master SSP I
2
C Bus Data Requirements
.................282
Master SSP I
2
C Bus START/STOP
Bits Requirements
............................................281
Oscillator Start-up Timer (OST)
...............................270
Parallel Slave Port (PSP)
.........................................274
Parallel Slave Port Requirements
............................274
PLL Clock
.................................................................269
Power-up Timer (PWRT)
..........................................270
RESET
.....................................................................270
RESET, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
Reset Requirements
........................................271
Timer0 and Timer1
.................................................. 272
Timer0 and Timer1 External
Clock Requirements
........................................ 272
USART Synchronous Receive
(Master/Slave)
................................................. 283
USART Synchronous Receive
Requirements
.................................................. 283
USART Synchronous Transmission
Requirements
.................................................. 283
USART Synchronous Transmission
(Master/Slave)
................................................. 283
Watchdog Timer (WDT)
........................................... 270
TRISE Register
.................................................................. 95
PSPMODE Bit
.......................................................93
,
98
TSTFSZ
........................................................................... 249
Two-Word Instructions
Example Cases
.......................................................... 41
TXSTA Register
BRGH Bit
................................................................. 166
U
Universal Synchronous Asynchronous Receiver
Transmitter.
See
USART.
USART
............................................................................. 163
Asynchronous Mode
................................................ 169
Associated Registers, Receive
........................ 172
Associated Registers, Transmit
....................... 170
Master Transmission
....................................... 170
Receive Block Diagram
................................... 171
Receiver
.......................................................... 171
Reception
........................................................ 172
Transmit Block Diagram
.................................. 169
Transmitter
....................................................... 169
Baud Rate Generator (BRG)
................................... 166
Associated Registers
....................................... 166
Baud Rate Error, Calculating
........................... 166
Baud Rate Formula
.......................................... 166
Baud Rates, Asynchronous Mode
(BRGH=0)
................................................ 167
Baud Rates, Asynchronous Mode
(BRGH=1)
................................................ 168
High Baud Rate Select (BRGH Bit)
................. 166
Sampling
.......................................................... 166
RCSTA Register
...................................................... 165
Serial Port Enable (SPEN Bit)
................................. 163
Synchronous Master Mode
...................................... 173
Associated Registers, Reception
..................... 175
Associated Registers, Transmit
....................... 173
Reception
........................................................ 175
Timing Diagram, Synchronous Receive
.......... 283
Timing Diagram, Synchronous
Transmission
........................................... 283
Transmission
................................................... 174
Associated Registers
............................... 173
Synchronous Slave Mode
........................................ 176
Associated Registers, Receive
........................ 177
Associated Registers, Transmit
....................... 176
Reception
........................................................ 177
Transmission
................................................... 176
TXSTA Register
....................................................... 164