參數(shù)資料
型號(hào)： PIC18F2321T-I/SS
廠商： Microchip Technology
文件頁數(shù)： 58/110頁
文件大?。?/td> 0K
描述： IC PIC MCU FLASH 4KX16 28SSOP
標(biāo)準(zhǔn)包裝： 2,100
系列： PIC® 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 40MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，HLVD，POR，PWM，WDT
輸入/輸出數(shù)： 25
程序存儲(chǔ)器容量： 8KB（4K x 16）
程序存儲(chǔ)器類型： 閃存
EEPROM 大小： 256 x 8
RAM 容量： 512 x 8
電壓 - 電源 (Vcc/Vdd)： 4.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
包裝： 帶卷 (TR)
2009 Microchip Technology Inc.
DS39689F-page 51
PIC18F2221/2321/4221/4321 FAMILY
5.5
Device Reset Timers
PIC18F2221/2321/4221/4321 family devices incorpo-
rate three separate on-chip timers that help regulate the
Power-on Reset process. Their main function is to
ensure that the device clock is stable before code is
executed. These timers are:
Power-up Timer (PWRT)
Oscillator Start-up Timer (OST)
PLL Lock Time-out
5.5.1
POWER-UP TIMER (PWRT)
The Power-up Timer (PWRT) of the PIC18F2221/
2321/4221/4321 family devices is an 11-bit counter
which uses the INTRC source as the clock input.
This yields an approximate time interval of
2048 x 32
μs = 65.6 ms. While the PWRT is counting,
the device is held in Reset.
The power-up time delay depends on the INTRC clock
and will vary from chip to chip due to temperature and
process variation. See DC parameter 33 for details.
The PWRT is enabled by clearing the PWRTEN
Configuration bit.
5.5.2
OSCILLATOR START-UP TIMER
(OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter 33). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP, HS and
HSPLL modes and only on Power-on Reset, or on exit
from most power-managed modes.
5.5.3
PLL LOCK TIME-OUT
With the PLL enabled in HSPLL mode, the time-out
sequence following a Power-on Reset is slightly differ-
ent from other oscillator modes. A separate timer is
used to provide a fixed time-out that is sufficient for the
PLL to lock to the main oscillator frequency. This PLL
lock time-out (TPLL) is typically 2 ms and follows the
oscillator start-up time-out.
5.5.4
TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows:
1.
After the POR pulse has cleared, PWRT time-out
is invoked (if enabled).
2.
Then, the OST is activated.
The total time-out will vary based on oscillator configu-
ration and the status of the PWRT. Figure 5-3,
depict time-out sequences on power-up, with the
Power-up Timer enabled and the device operating in
HS Oscillator mode. Figures 5-3 through 5-6 also
apply to devices operating in XT or LP modes. For
devices in RC mode and with the PWRT disabled, there
will be no time-out at all.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, all time-outs will expire. Bring-
ing MCLR high will begin execution immediately
(Figure 5-5). This is useful for testing purposes or to
synchronize more than one PIC18FXXXX device
operating in parallel.
TABLE 5-2:
TIME-OUT IN VARIOUS SITUATIONS
Oscillator
Configuration
Power-up(2) and Brown-out Reset
Exit from
Power-Managed Mode
PWRTEN = 0
PWRTEN = 1
HSPLL
66 ms(1) + 1024 TOSC + 2 ms(2)
1024 TOSC + 2 ms(2)
HS, XT, LP
66 ms(1) + 1024 TOSC
1024 TOSC
EC, ECIO
66 ms(1)
——
RC, RCIO
66 ms(1)
——
INTIO1, INTIO2
66 ms(1)
——
Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2: 2 ms is the nominal time required for the PLL to lock.
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