參數(shù)資料
型號(hào): PIC18F2321T-I/SS
廠商: Microchip Technology
文件頁(yè)數(shù): 52/110頁(yè)
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 4KX16 28SSOP
標(biāo)準(zhǔn)包裝: 2,100
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,HLVD,POR,PWM,WDT
輸入/輸出數(shù): 25
程序存儲(chǔ)器容量: 8KB(4K x 16)
程序存儲(chǔ)器類型: 閃存
EEPROM 大小: 256 x 8
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
包裝: 帶卷 (TR)
PIC18F2221/2321/4221/4321 FAMILY
DS39689F-page 46
2009 Microchip Technology Inc.
4.5.4
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
PRI_IDLE mode, where the primary clock source
is not stopped; and
the primary clock source is not any of the LP, XT,
HS or HSPLL modes.
In these instances, the primary clock source either
does not require an oscillator start-up delay since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (RC, EC and INTIO
Oscillator modes). However, a fixed delay of interval
TCSD following the wake event is still required when
leaving Sleep and Idle modes to allow the CPU to
prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.
TABLE 4-2:
EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Clock Source
before Wake-up
Clock Source
after Wake-up
Exit Delay
Clock Ready Status
Bit (OSCCON)
Primary Device Clock
(PRI_IDLE mode)
LP, XT, HS
TCSD(1)
OSTS
HSPLL
EC, RC
INTOSC(2)
IOFS
T1OSC
LP, XT, HS
TOST(3)
OSTS
HSPLL
TOST + trc(3)
EC, RC
TCSD(1)
INTOSC(2)
TIOBST(4)
IOFS
INTOSC(3)
LP, XT, HS
TOST(3)
OSTS
HSPLL
TOST + trc(3)
EC, RC
TCSD(1)
INTOSC(2)
None
IOFS
None
(Sleep mode)
LP, XT, HS
TOST(3)
OSTS
HSPLL
TOST + trc(3)
EC, RC
TCSD(1)
INTOSC(2)
TIOBST(4)
IOFS
Note 1:
TCSD (parameter 38) is a required delay when waking from Sleep and all Idle modes and runs concurrently
with any other required delays (see Section 4.4 “Idle Modes”). On Reset, INTOSC defaults to 1 MHz.
2:
Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
3:
TOST is the Oscillator Start-up Timer (parameter 32). trc is the PLL Lock-out Timer (parameter F12); it is
also designated as TPLL.
4:
Execution continues during TIOBST (parameter 39), the INTOSC stabilization period.
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