2007 Microchip Technology Inc.
Preliminary
DS39689E-page 389
PIC18F4321 FAMILY
BRG Reset Due to SDA Arbitration
During Start Condition .....................................201
Brown-out Reset (BOR) ...........................................350
Bus Collision During a Repeated
Start Condition (Case 1) ..................................202
Bus Collision During a Repeated
Start Condition (Case 2) ..................................202
Bus Collision During a
Start Condition (SCL = 0) .................................201
Bus Collision During a
Stop Condition (Case 1) ..................................203
Bus Collision During a
Stop Condition (Case 2) ..................................203
Bus Collision During
Start Condition (SDA Only) ..............................200
Bus Collision for Transmit and
Acknowledge ...................................................199
Capture/Compare/PWM (All CCP Modules) ............352
CLKO and I/O ..........................................................349
Clock Synchronization .............................................185
Clock/Instruction Cycle ..............................................57
EUSART Synchronous Receive
(Master/Slave) .................................................362
EUSART Synchronous Transmission
(Master/Slave) .................................................362
Example SPI Master Mode (CKE = 0) .....................354
Example SPI Master Mode (CKE = 1) .....................355
Example SPI Slave Mode (CKE = 0) .......................356
Example SPI Slave Mode (CKE = 1) .......................357
External Clock (All Modes Except PLL) ...................347
Fail-Safe Clock Monitor ............................................267
First Start Bit Timing ................................................193
Full-Bridge PWM Output ..........................................153
Half-Bridge PWM Output .........................................152
High/Low-Voltage Detect Characteristics ................344
High-Voltage Detect Operation
(VDIRMAG = 1) ................................................250
I
2
C Bus Data ............................................................358
I
2
C Bus Start/Stop Bits .............................................358
I
2
C Master Mode (7 or 10-Bit Transmission) ...........196
I
2
C Master Mode (7-Bit Reception) ..........................197
I
2
C Slave Mode (10-Bit Reception, SEN = 0) ..........182
I
2
C Slave Mode (10-Bit Reception,
SEN = 0, ADMSK = 01001) .............................181
I
2
C Slave Mode (10-Bit Reception,
SEN = 1) ..........................................................187
I
2
C Slave Mode (10-Bit Transmission) .....................183
I
2
C Slave Mode (7-Bit Reception,
SEN = 0) ..........................................................178
I
2
C Slave Mode (7-bit Reception,
SEN = 0, ADMSK = 01011) .............................179
I
2
C Slave Mode (7-Bit Reception, SEN = 1) ............186
I
2
C Slave Mode (7-Bit Transmission) .......................180
I
2
C Slave Mode General Call Address
Sequence (7 or 10-Bit Address Mode) ............188
I
2
C Stop Condition Receive or
Transmit Mode .................................................198
Low-Voltage Detect Operation (VDIRMAG = 0) ......249
Master SSP I
2
C Bus Data ........................................360
Master SSP I
2
C Bus Start/Stop Bits ........................360
Parallel Slave Port (PIC18F4221/4321) ...................353
Parallel Slave Port (PSP) Read ...............................121
Parallel Slave Port (PSP) Write ...............................121
PWM Auto-Shutdown (PRSEN = 0,
Auto-Restart Disabled) ....................................158
PWM Auto-Shutdown (PRSEN = 1,
Auto-Restart Enabled) ..................................... 158
PWM Direction Change ........................................... 155
PWM Direction Change at Near
100% Duty Cycle ............................................. 155
PWM Output ............................................................ 144
Repeat Start Condition ............................................ 194
Reset, Watchdog Timer (WDT), Oscillator
Start-up Timer (OST),
Power-up Timer (PWRT) ................................. 350
Send Break Character Sequence ............................ 221
Slave Synchronization ............................................. 167
Slow Rise Time (MCLR Tied to V
DD
,
V
DD
Rise > T
PWRT
) ............................................ 47
SPI Mode (Master Mode) ........................................ 166
SPI Mode (Slave Mode, CKE = 0) ........................... 168
SPI Mode (Slave Mode, CKE = 1) ........................... 168
Synchronous Reception
(Master Mode, SREN) ..................................... 224
Synchronous Transmission ..................................... 222
Synchronous Transmission (Through TXEN) .......... 223
Time-out Sequence on POR w/PLL Enabled
(MCLR Tied to V
DD
) .......................................... 47
Time-out Sequence on Power-up
(MCLR Not Tied to V
DD
, Case 1) ...................... 46
Time-out Sequence on Power-up
(MCLR Not Tied to V
DD
, Case 2) ...................... 46
Time-out Sequence on Power-up
(MCLR Tied to V
DD
, V
DD
Rise < T
PWRT
) ........... 46
Timer0 and Timer1 External Clock .......................... 351
Transition for Entry to Idle Mode ............................... 38
Transition for Entry to SEC_RUN Mode .................... 35
Transition for Entry to Sleep Mode ............................ 37
Transition for Two-Speed Start-up
(INTOSC to HSPLL) ........................................ 265
Transition for Wake from Idle to Run Mode ............... 38
Transition for Wake from Sleep (HSPLL) .................. 37
Transition from RC_RUN Mode to
PRI_RUN Mode ................................................. 36
Transition from SEC_RUN Mode to
PRI_RUN Mode (HSPLL) .................................. 35
Transition to RC_RUN Mode ..................................... 36
Timing Diagrams and Specifications ............................... 347
Capture/Compare/PWM Requirements
(All CCP Modules) ........................................... 352
CLKO and I/O Requirements ................................... 349
EUSART Synchronous Receive
Requirements .................................................. 362
EUSART Synchronous Transmission
Requirements .................................................. 362
Example SPI Mode Requirements
(Master Mode, CKE = 0) .................................. 354
Example SPI Mode Requirements
(Master Mode, CKE = 1) .................................. 355
Example SPI Mode Requirements
(Slave Mode, CKE = 0) .................................... 356
Example SPI Mode Requirements
(Slave Mode, CKE = 1) .................................... 357
External Clock Requirements .................................. 347
I
2
C Bus Data Requirements (Slave Mode) .............. 359
Master SSP I
2
C Bus Data Requirements ................ 361
Master SSP I
2
C Bus Start/Stop Bits
Requirements .................................................. 360
Parallel Slave Port Requirements
(PIC18F4221/4321) ......................................... 353