
PIC18F4321 FAMILY
DS39689E-page 382
Preliminary
2007 Microchip Technology Inc.
BSF ..................................................................................285
BTFSC .............................................................................286
BTFSS ..............................................................................286
BTG ..................................................................................287
BZ .....................................................................................288
C
C Compilers
MPLAB C18 .............................................................324
MPLAB C30 .............................................................324
CALL ................................................................................288
CALLW .............................................................................317
Capture (CCP Module) .....................................................141
Associated Registers ...............................................143
CCP Pin Configuration .............................................141
CCPRxH:CCPRxL Registers ...................................141
Prescaler ..................................................................141
Software Interrupt ....................................................141
Timer1/Timer3 Mode Selection ................................141
Capture (ECCP Module) ..................................................148
Capture/Compare/PWM (CCP) ........................................139
Capture Mode.
See
Capture.
CCPRxH Register ....................................................140
CCPRxL Register .....................................................140
Compare Mode.
See
Compare.
Interaction of Two CCP Modules .............................140
Module Configuration ...............................................140
Pin Assignment ........................................................140
Timer Resources ......................................................140
Clock Sources ....................................................................29
Selecting the 31 kHz Source ......................................30
Selection Using OSCCON Register ...........................30
CLRF ................................................................................289
CLRWDT ..........................................................................289
Code Examples
16 x 16 Signed Multiply Routine ................................90
16 x 16 Unsigned Multiply Routine ............................90
8 x 8 Signed Multiply Routine ....................................89
8 x 8 Unsigned Multiply Routine ................................89
Address Masking .....................................................176
Changing Between Capture Prescalers ...................141
Computed GOTO Using an Offset Value ...................56
Data EEPROM Read .................................................85
Data EEPROM Refresh Routine ................................86
Data EEPROM Write .................................................85
Erasing a Flash Program Memory Row .....................78
Fast Register Stack ....................................................56
How to Clear RAM (Bank 1) Using
Indirect Addressing ............................................67
Implementing a Real-Time Clock
Using a Timer1 Interrupt Service .....................131
Initializing PORTA ....................................................105
Initializing PORTB ....................................................108
Initializing PORTC ....................................................111
Initializing PORTD ....................................................114
Initializing PORTE ....................................................117
Loading the SSPBUF (SSPSR) Register .................164
Reading a Flash Program Memory Word ..................77
Saving STATUS, WREG and
BSR Registers in RAM .....................................103
Writing to Flash Program Memory .......................80–81
Code Protection .......................................................253, 268
Associated Registers ...............................................269
Configuration Register Protection ............................271
Data EEPROM .........................................................271
Program Memory .....................................................269
COMF .............................................................................. 290
Comparator ...................................................................... 237
Analog Input Connection Considerations ................ 241
Associated Registers ............................................... 241
Configuration ........................................................... 238
Effects of a Reset .................................................... 240
Interrupts ................................................................. 240
Operation ................................................................. 239
Operation During Sleep ........................................... 240
Outputs .................................................................... 239
Reference ................................................................ 239
External Signal ................................................ 239
Internal Signal .................................................. 239
Response Time ........................................................ 239
Comparator Specifications ............................................... 343
Comparator Voltage Reference ....................................... 243
Accuracy and Error .................................................. 244
Associated Registers ............................................... 245
Configuring .............................................................. 243
Connection Considerations ...................................... 244
Effects of a Reset .................................................... 244
Operation During Sleep ........................................... 244
Compare (CCP Module) .................................................. 142
Associated Registers ............................................... 143
CCPRx Register ...................................................... 142
Pin Configuration ..................................................... 142
Software Interrupt .................................................... 142
Special Event Trigger .............................. 137, 142, 236
Timer1/Timer3 Mode Selection ................................ 142
Compare (ECCP Module) ................................................ 148
Special Event Trigger .............................................. 148
Computed GOTO ............................................................... 56
Configuration Bits ............................................................ 253
Context Saving During Interrupts ..................................... 103
Conversion Considerations .............................................. 378
CPFSEQ .......................................................................... 290
CPFSGT .......................................................................... 291
CPFSLT ........................................................................... 291
Crystal Oscillator/Ceramic Resonator ................................ 23
Customer Change Notification Service ............................ 391
Customer Notification Service ......................................... 391
Customer Support ............................................................ 391
D
Data Addressing Modes .................................................... 67
Comparing Options with the
Extended Instruction Set Enabled ..................... 70
Direct ......................................................................... 67
Indexed Literal Offset ................................................ 69
Instructions Affected .......................................... 69
Indirect ....................................................................... 67
Inherent and Literal .................................................... 67
Data EEPROM Memory ..................................................... 83
Associated Registers ................................................. 87
EEADR Register ........................................................ 83
EECON1 and EECON2 Registers ............................. 83
EEDATA Register ...................................................... 83
Operation During Code-Protect ................................. 86
Protection Against Spurious Write ............................. 86
Reading ..................................................................... 85
Using ......................................................................... 86
Write Verify ................................................................ 85
Writing ....................................................................... 85