
PIC18F1230/1330
DS39758D-page 178
2009 Microchip Technology Inc.
TABLE 16-2:
REGISTERS ASSOCIATED WITH A/D OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
PIR1
—ADIF
RCIF
TXIF
CMP2IF
CMP1IF
CMP0IF
TMR1IF
PIE1
—ADIE
RCIE
TXIE
CMP2IE
CMP1IE
CMP0IE
TMR1IE
IPR1
—ADIP
RCIP
TXIP
CMP2IP
CMP1IP
CMP0IP
TMR1IP
ADRESH
A/D Result Register High Byte
ADRESL
A/D Result Register Low Byte
ADCON0
SEVTEN
—
CHS1
CHS0
GO/DONE
ADON
ADCON1
—
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
ADCON2
ADFM
—
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
PORTA
RA7(1)
RA6(1)
RA5(2)
RA4
RA3
RA2
RA1
RA0
TRISA
TRISA7(1) TRISA6(1) PORTA Data Direction Control Register
Legend:
— = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1:
PORTA<7:6> and their direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
2:
The RA5 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0);
otherwise, RA5 reads as ‘0’. This bit is read-only.