PIC18F1230/1330
2009 Microchip Technology Inc.
DS39758D-page 197
REGISTER 20-6:
CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)
R/P-1
R/P-0
U-0
R/P-1
BKBUG
XINST
BBSIZ1
BBSIZ0
—
—STVREN
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7
BKBUG:
Background Debugger Enable bit
1
= Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
0
= Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
bit 6
XINST:
Extended Instruction Set Enable bit
1
= Instruction set extension and Indexed Addressing mode enabled
0
= Instruction set extension and Indexed Addressing mode disabled
bit 5-4
BBSIZ<1:0>:
Boot Block Size Select bits
For PIC18F1330 device:
11
= 1 kW Boot Block size
10
= 1 kW Boot Block size
01
= 512W Boot Block size
00
= 256W Boot Block size
For PIC18F1230 device:
11
= 512W Boot Block size
10
= 512W Boot Block size
01
= 512W Boot Block size
00
= 256W Boot Block size
bit 3
Unimplemented:
Maintain as ‘0’
bit 2-1
Unimplemented:
Read as ‘0’
bit 0
STVREN:
Stack Overflow/Underflow Reset Enable bit
1
= Reset on stack overflow/underflow enabled
0
= Reset on stack overflow/underflow disabled
