PIC18F1230/1330
DS39758D-page 170
2009 Microchip Technology Inc.
REGISTER 16-2:
ADCON1: A/D CONTROL REGISTER 1
U-0
R/W-0
—
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented:
Read as ‘0’
bit 4
VCFG0:
Voltage Reference Configuration bit (VREF+ source)
1
= Positive reference for the A/D is VREF+
0
= Positive reference for the A/D is AVDD
bit 3
PCFG3:
A/D Port Configuration bit for RA6/AN3
0
= Port is configured as AN3
1
= Port is configured as RA6
bit 2
PCFG2:
A/D Port Configuration bit for RA4/AN2
0
= Port is configured as AN2
1
= Port is configured as RA4
bit 1
PCFG1:
A/D Port Configuration bit for RA1/AN1
0
= Port is configured as AN1
1
= Port is configured as RA1
bit 0
PCFG0:
A/D Port Configuration bit for RA0/AN0
0
= Port is configured as AN0
1
= Port is configured as RA0