
PIC18F1230/1330
DS39758D-page 196
2009 Microchip Technology Inc.
REGISTER 20-5:
CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
R/P-1
U-0
R/P-0
U-0
R/P-1
MCLRE
—
—T1OSCMX
—
—FLTAMX
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7
MCLRE:
MCLR Pin Enable bit
1
=MCLR pin enabled, RA5 input pin disabled
0
= RA5 input pin enabled, MCLR pin disabled
bit 6-4
Unimplemented:
Read as ‘0’
bit 3
T1OSCMX:
T1OSO/T1CKI MUX bit
1
= T1OSO/T1CKI pin resides on RA6
0
= T1OSO/T1CKI pin resides on RB2
bit 2-1
Unimplemented:
Read as ‘0’
bit 0
FLTAMX:
FLTA MUX bit
1
= FLTA is muxed onto RA5
0
= FLTA is muxed onto RA7