參數(shù)資料
型號： PIC17LC766-08/PT
廠商： Microchip Technology
文件頁數(shù)： 109/159頁
文件大?。?/td> 0K
描述： IC MCU OTP 16KX16 A/D PWM 80TQFP
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
標準包裝： 119
系列： PIC® 17C
核心處理器： PIC
芯體尺寸： 8-位
速度： 8MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 66
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： OTP
RAM 容量： 902 x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x10b
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 80-TQFP
包裝： 托盤
PIC17C7XX
DS30289B-page 52
2000 Microchip Technology Inc.
7.2.2.2
CPU Status Register (CPUSTA)
The CPUSTA register contains the status and control
bits for the CPU. This register has a bit that is used to
globally enable/disable interrupts. If only a specific
interrupt is desired to be enabled/disabled, please refer
to the Interrupt Status (INTSTA) register and the
Peripheral Interrupt Enable (PIE) registers. The
CPUSTA register also indicates if the stack is available
and contains the Power-down (PD) and Time-out (TO)
bits. The TO, PD, and STKAV bits are not writable.
These bits are set and cleared according to device
logic. Therefore, the result of an instruction with the
CPUSTA register as destination may be different than
intended.
The POR bit allows the differentiation between a
Power-on Reset, external MCLR Reset, or a WDT
Reset. The BOR bit indicates if a Brown-out Reset
occurred.
REGISTER 7-2:
CPUSTA REGISTER (ADDRESS: 06h, UNBANKED)
Note 1: The BOR status bit is a don’t care and is
not necessarily predictable if the Brown-out
circuit is disabled (when the BODEN bit in
the Configuration word is programmed).
U-0
R-1
R/W-1
R-1
R/W-0
R/W-1
—
STKAV
GLINTD
TO
PD
POR
BOR
bit 7
bit 0
bit 7-6
Unimplemented: Read as '0'
bit 5
STKAV: Stack Available bit
This bit indicates that the 4-bit stack pointer value is Fh, or has rolled over from Fh
→ 0h
(stack overflow).
1
= Stack is available
0
= Stack is full, or a stack overflow may have occurred (once this bit has been cleared by a
stack overflow, only a device RESET will set this bit)
bit 4
GLINTD: Global Interrupt Disable bit
This bit disables all interrupts. When enabling interrupts, only the sources with their enable bits
set can cause an interrupt.
1
= Disable all interrupts
0
= Enables all unmasked interrupts
bit 3
TO: WDT Time-out Status bit
1
= After power-up, by a CLRWDT instruction, or by a SLEEP instruction
0
= A Watchdog Timer time-out occurred
bit 2
PD: Power-down Status bit
1
= After power-up or by the CLRWDT instruction
0
= By execution of the SLEEP instruction
bit 1
POR: Power-on Reset Status bit
1
= No Power-on Reset occurred
0
= A Power-on Reset occurred (must be set by software)
bit 0
BOR: Brown-out Reset Status bit
When BODEN Configuration bit is set (enabled):
1
= No Brown-out Reset occurred
0
= A Brown-out Reset occurred (must be set by software)
When BODEN Configuration bit is clear (disabled):
Don’t care
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR Reset
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
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