參數(shù)資料
型號： PIC17LC766-08/PT
廠商： Microchip Technology
文件頁數(shù)： 108/159頁
文件大小： 0K
描述： IC MCU OTP 16KX16 A/D PWM 80TQFP
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
標準包裝： 119
系列： PIC® 17C
核心處理器： PIC
芯體尺寸： 8-位
速度： 8MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 66
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： OTP
RAM 容量： 902 x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x10b
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 80-TQFP
包裝： 托盤
2000 Microchip Technology Inc.
DS30289B-page 51
PIC17C7XX
7.2.2.1
ALU Status Register (ALUSTA)
The ALUSTA register contains the status bits of the
Arithmetic and Logic Unit and the mode control bits for
the indirect addressing register.
As with all the other registers, the ALUSTA register can
be the destination for any instruction. If the ALUSTA
register is the destination for an instruction that affects
the Z, DC, C, or OV bits, then the write to these three
bits is disabled. These bits are set or cleared according
to the device logic. Therefore, the result of an instruc-
tion with the ALUSTA register as destination may be
different than intended.
For example, the CLRF ALUSTA, F instruction will clear
the upper four bits and set the Z bit. This leaves the
ALUSTA register as 0000u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF, SWAPF
and MOVWF instructions be used to alter the ALUSTA
register, because these instructions do not affect any
status bits. To see how other instructions affect the sta-
tus bits, see the “Instruction Set Summary.”
The Arithmetic and Logic Unit (ALU) is capable of car-
rying out arithmetic or logical operations on two oper-
ands, or a single operand. All single operand
instructions operate either on the WREG register, or
the given file register. For two operand instructions, one
of the operands is the WREG register and the other is
either a file register, or an 8-bit immediate constant.
REGISTER 7-1:
ALUSTA REGISTER (ADDRESS: 04h, UNBANKED)
Note 1: The C and DC bits operate as a borrow and
digit borrow bit, respectively, in subtraction.
See the SUBLW and SUBWF instructions for
examples.
2: The overflow bit will be set if the 2’s comple-
ment result exceeds +127, or is less than -128.
R/W-1
R/W-x
FS3
FS2
FS1
FS0
OV
Z
DC
C
bit 7
bit 0
bit 7-6
FS3:FS2: FSR1 Mode Select bits
00
= Post auto-decrement FSR1 value
01
= Post auto-increment FSR1 value
1x
= FSR1 value does not change
bit 5-4
FS1:FS0: FSR0 Mode Select bits
00
= Post auto-decrement FSR0 value
01
= Post auto-increment FSR0 value
1x
= FSR0 value does not change
bit 3
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit
magnitude, which causes the sign bit (bit7) to change state.
1
= Overflow occurred for signed arithmetic (in this arithmetic operation)
0
= No overflow occurred
bit 2
Z: Zero bit
1
= The result of an arithmetic or logic operation is zero
0
= The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit carry/borrow bit
For ADDWF and ADDLW instructions.
1
= A carry-out from the 4th low order bit of the result occurred
0
= No carry-out from the 4th low order bit of the result
Note:
For borrow, the polarity is reversed.
bit 0
C: Carry/borrow bit
For ADDWF and ADDLW instructions. Note that a subtraction is executed by adding the two’s
complement of the second operand.
For rotate (RRCF, RLCF) instructions, this bit is loaded with either the high or low order bit of the
source register.
1
= A carry-out from the Most Significant bit of the result occurred
0
= No carry-out from the Most Significant bit of the result
Note:
For borrow, the polarity is reversed.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR Reset
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
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