參數(shù)資料
型號: PIC17C766-33E/L
廠商: Microchip Technology
文件頁數(shù): 68/159頁
文件大?。?/td> 0K
描述: IC MCU CMOS 33MHZ 16K EPRM84PLCC
標準包裝: 16
系列: PIC® 17C
核心處理器: PIC
芯體尺寸: 8-位
速度: 33MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 66
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: OTP
RAM 容量: 902 x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
振蕩器型: 外部
工作溫度: -40°C ~ 125°C
封裝/外殼: 84-LCC(J 形引線)
包裝: 管件
配用: AC164318-ND - MODULE SKT MPLAB PM3 84PLCC
DVA17XL841-ND - DEVICE ADAPTER FOR PIC17C762
DM173001-ND - KIT DEVELOPMENT PICDEM17
AC164027-ND - ADAPTER PICSTART PLUS 84PLCC
AC174012-ND - MODULE SKT PROMATEII 84PLCC
2000 Microchip Technology Inc.
DS30289B-page 23
PIC17C7XX
5.0
RESET
The PIC17CXXX differentiates between various kinds
of RESET:
Power-on Reset (POR)
Brown-out Reset
MCLR Reset
WDT Reset
Some registers are not affected in any RESET condi-
tion, their status is unknown on POR and unchanged in
any other RESET. Most other registers are forced to a
“RESET state”. The TO and PD bits are set or cleared
differently in different RESET situations, as indicated in
Table 5-3. These bits, in conjunction with the POR and
BOR bits, are used in software to determine the nature
of the RESET. See Table 5-4 for a full description of the
RESET states of all registers.
When the device enters the “RESET state”, the Data
Direction registers (DDR) are forced set, which will
make the I/O hi-impedance inputs. The RESET state of
some peripheral modules may force the I/O to other
operations, such as analog inputs or the system bus.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 5-1.
FIGURE 5-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Note:
While the device is in a RESET state, the
internal phase clock is held in the Q1 state.
Any processor mode that allows external
execution will force the RE0/ALE pin as a
low output and the RE1/OE and RE2/WR
pins as high outputs.
S
R
Q
External
Reset
MCLR
VDD
OSC1
WDT
Module
VDD Rise
Detect
OST/PWRT
On-chip
RC OSC
WDT
Time_Out
Power_On_Reset
OST
10-bit Ripple Counter
PWRT
Chip_Reset
10-bit Ripple Counter
(Enable the PWRT timer
only during POR or BOR)
(If PWRT is invoked, or a Wake-up from
SLEEP and OSC type is XT or LF)
Reset
E
nable
O
S
T
Enable
PW
R
T
This RC oscillator is shared with the WDT when not in a power-up sequence.
BOR
Module
Brown-out
Reset
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