1996 Microchip Technology Inc.
DS30412B-page 229
PIC17C4X
Turning on 16-bit Timer ......................................................74
TX9 ....................................................................................83
TX9d ..................................................................................83
TXEN .................................................................................83
TXIE ...................................................................................23
TXIF ...................................................................................24
TXREG .................................................19, 34, 89, 93, 97, 98
TXSTA .......................................................19, 34, 92, 96, 98
U
Upward Compatibility ...........................................................5
USART
Asynchronous Master Transmission ..........................90
Asynchronous Mode ..................................................89
Asynchronous Receive ..............................................91
Asynchronous Transmitter .........................................89
Baud Rate Generator .................................................86
Synchronous Master Mode ........................................93
Synchronous Master Reception .................................95
Synchronous Master Transmission ............................93
Synchronous Slave Mode ..........................................97
Synchronous Slave Transmit .....................................97
W
Wake-up from SLEEP ......................................................105
Wake-up from SLEEP Through Interrupt .........................105
Watchdog Timer .........................................................99, 103
WDT ...........................................................................99, 103
Clearing the WDT ....................................................103
Normal Timer ...........................................................103
Period .......................................................................103
Programming Considerations ..................................103
WDTPS0 ............................................................................99
WDTPS1 ............................................................................99
WREG ................................................................................34
X
XORLW ............................................................................141
XORWF ............................................................................141
Z
Z .....................................................................................9, 36
Zero (Z) ................................................................................9
LIST OF EXAMPLES
Example 3-1: Signed Math..................................................9
Example 3-2: Instruction Pipeline Flow .............................14
Example 5-1: Saving STATUS and WREG in RAM..........27
Example 6-1: Indirect Addressing......................................40
Example 7-1: Table Write..................................................46
Example 7-2: Table Read..................................................48
Example 8-1: 8 x 8 Multiply Routine..................................49
Example 8-2: 8 x 8 Signed Multiply Routine......................49
Example 8-3: 16 x 16 Multiply Routine..............................50
Example 8-4: 16 x 16 Signed Multiply Routine..................51
Example 9-1: Initializing PORTB.......................................57
Example 9-2: Initializing PORTC.......................................58
Example 9-3: Initializing PORTD.......................................60
Example 9-4: Initializing PORTE.......................................62
Example 9-5: Read Modify Write Instructions on an
I/O Port........................................................64
Example 11-1: 16-Bit Read .................................................69
Example 11-2: 16-Bit Write..................................................69
Example 12-1: Sequence to Read Capture Registers.........78
Example 12-2: Writing to TMR3 ..........................................80
Example 12-3: Reading from TMR3....................................80
Example 13-1: Calculating Baud Rate Error........................86
Example F-1: PIC17C42 to Sleep....................................221
LIST OF FIGURES
Figure 3-1:
Figure 3-2:
PIC17C42 Block Diagram ...........................10
PIC17CR42/42A/43/R43/44 Block
Diagram.......................................................11
Clock/Instruction Cycle................................14
Simplified Block Diagram of On-chip
Reset Circuit................................................15
Time-Out Sequence on Power-Up
(MCLR Tied to V
DD
)...................................17
Time-Out Sequence on Power-Up
(MCLR
NOT
Tied to V
DD
Slow Rise Time (MCLR Tied to V
Oscillator Start-Up Time..............................18
Using On-Chip POR....................................18
Brown-out Protection Circuit 1.....................18
PIC17C42 External Power-On Reset
Circuit (For Slow V
DD
Power-Up)................18
Brown-out Protection Circuit 2.....................18
Interrupt Logic .............................................21
INTSTA Register (Address: 07h,
Unbanked)...................................................22
PIE Register (Address: 17h, Bank 1) ..........23
PIR Register (Address: 16h, Bank 1)..........24
INT Pin / T0CKI Pin Interrupt Timing...........26
Program Memory Map and Stack................29
Memory Map in Different Modes.................30
External Program Memory Access
Waveforms..................................................31
Typical External Program Memory
Connection Diagram...................................31
PIC17C42 Register File Map.......................33
PIC17CR42/42A/43/R43/44 Register
File Map......................................................33
ALUSTA Register (Address: 04h,
Unbanked)...................................................36
CPUSTA Register (Address: 06h,
Unbanked)...................................................37
T0STA Register (Address: 05h,
Unbanked)...................................................38
Indirect Addressing......................................39
Program Counter Operation........................41
Figure 3-3:
Figure 4-1:
Figure 4-2:
Figure 4-3:
)............................17
DD
Figure 4-4:
Figure 4-5:
Figure 4-6:
Figure 4-7:
Figure 4-8:
)..........17
Figure 4-9:
Figure 5-1:
Figure 5-2:
Figure 5-3:
Figure 5-4:
Figure 5-5:
Figure 6-1:
Figure 6-2:
Figure 6-3:
Figure 6-4:
Figure 6-5:
Figure 6-6:
Figure 6-7:
Figure 6-8:
Figure 6-9:
Figure 6-10:
Figure 6-11: