2001 Microchip Technology Inc.
DS30292C-page 77
PIC16F87X
9.2.3
SLEEP OPERATION
While in SLEEP mode, the I2C module can receive
addresses or data. When an address match or com-
plete byte transfer occurs, wake the processor from
SLEEP (if the SSP interrupt is enabled).
9.2.4
EFFECTS OF A RESET
A RESET disables the SSP module and terminates the
current transfer.
TABLE 9-3:
REGISTERS ASSOCIATED WITH I2C OPERATION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on:
MCLR,
WDT
0Bh, 8Bh,
10Bh,18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
0Dh
PIR2
—
(2)
—
EEIF
BCLIF
—
CCP2IF -r-0 0--0 -r-0 0--0
8Dh
PIE2
—
(2)
—
EEIE
BCLIE
—
CCP2IE -r-0 0--0 -r-0 0--0
13h
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx
uuuu uuuu
14h
SSPCON
WCOL
SSPOV
SSPEN
CKP
SSPM3 SSPM2
SSPM1
SSPM0
0000 0000
91h
SSPCON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
0000 0000
93h
SSPADD
I2C Slave Address/Master Baud Rate Register
0000 0000
94h
SSPSTAT
SMP
CKE
D/A
PS
R/W
UA
BF
0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the SSP in I2C mode.
Note 1: These bits are reserved on PIC16F873/876 devices; always maintain these bits clear.
2: These bits are reserved on these devices; always maintain these bits clear.