參數(shù)資料
型號: PIC16LF1933-E/SP
廠商: Microchip Technology
文件頁數(shù): 5/40頁
文件大小: 0K
描述: MCU PIC 8BIT 4K FLASH 28SDIP
標準包裝: 15
系列: PIC® XLP™ 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 32MHz
連通性: I²C,LIN,SPI,UART/USART
外圍設備: 欠壓檢測/復位,LCD,POR,PWM,WDT
輸入/輸出數(shù): 25
程序存儲器容量: 7KB(4K x 14)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 11x10b
振蕩器型: 內部
工作溫度: -40°C ~ 125°C
封裝/外殼: 28-DIP(0.300",7.62mm)
包裝: 管件
2008 Microchip Technology Inc.
Advance Information
DS41360A-page 13
PIC16F193X/LF193X
4.0
PROGRAM/VERIFY MODE
In Program/Verify mode, the program memory and the
configuration memory can be accessed and pro-
grammed in serial fashion. ICSPDAT and ICSPCLK
are used for the data and the clock, respectively. All
commands and data words are transmitted LSb first.
Data changes on the rising edge of the ICSPCLK and
latched on the falling edge. In Program/Verify mode
both the ICSPDAT and ICSPCLK are Schmitt Trigger
inputs. The sequence that enters the device into
Program/Verify mode places all other logic into the
Reset state. Upon entering Program/Verify mode, all
I/O’s are automatically configured as high-impedance
inputs and the address is cleared.
4.1
High-Voltage Program/Verify Mode
Entry and Exit
There
are
two
different
methods
of
entering
Program/Verify mode via high-voltage:
VPP – First entry mode
VDD – First entry mode
4.1.1
VPP – FIRST ENTRY MODE
To enter Program/Verify mode via the VPP-first method
the following sequence must be followed:
1.
Hold ICSPCLK and ICSPDAT low. All other pins
should be unpowered.
2.
Raise the voltage on MCLR from 0V to VIHH.
3.
Raise the voltage on VDD FROM 0V to the
desired operating voltage.
The VPP-first entry prevents the device from executing
code prior to entering Program/Verify mode. For
example, when the Configuration Word has MCLR
disabled (MCLRE = 0), the power-up time is disabled
(PWRTE = 0),
the
internal
oscillator
is
selected
(FOSC = 100), and RB6 and RB7 are driven by the user
application, the device will execute code. Since this
may prevent entry, VPP-first entry mode is strongly
recommended. See the timing diagram in Figure 8-3.
4.1.2
VDD – FIRST ENTRY MODE
To enter Program/Verify mode via the VDD-first method
the following sequence must be followed:
1.
Hold ICSPCLK and ICSPDAT low.
2.
Raise the voltage on VDD from 0V to the desired
operating voltage.
3.
Raise the voltage on MCLR from VDD or below
to VIHH.
The VDD-first method is useful when programming the
device when VDD is already applied, for it is not neces-
sary to disconnect VDD to enter Program/Verify mode.
See the timing diagram in Figure 8-2.
4.1.3
PROGRAM/VERIFY MODE EXIT
To exit Program/Verify mode take MCLR to VDD or
lower (VIL). See Figures 8-4 and 8-5.
4.2
Low-Voltage Programming (LVP)
Mode
The Low-Voltage Programming mode allows the
PIC16F193X/LF193X devices to be programmed using
VDD only, without high voltage. When the LVP bit of the
Configuration Word 2 register is set to '1', the
low-voltage ICSP programming entry is enabled. To
disable the Low-Voltage ICSP mode, the LVP bit must
be programmed to '0'. This can only be done while in
the High-Voltage Entry mode.
Entry into the Low-Voltage ICSP Program/Verify modes
requires the following steps:
1.
MCLR is brought to VIL.
2.
A
32-bit
key
sequence
is
presented
on
ICSPDAT, while clocking ICSPCLK.
The key sequence is a specific 32-bit pattern, '0100
1101 0100 0011 0100 1000 0101 0000'
(more
easily remembered as MCHP in ASCII). The device will
enter Program/Verify mode only if the sequence is
valid. The Least Significant bit of the Least Significant
nibble must be shifted in first.
Once the key sequence is complete, MCLR must be
held at VIL for as long as Program/Verify mode is to be
maintained.
For low-voltage programming timing, see Figures 8-9
and 8-10.
Exiting Program/Verify mode is done by no longer
driving MCLR to VIL. See Figures 8-9 and 8-10.
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