參數(shù)資料
型號(hào): PIC16LF1933-E/SP
廠商: Microchip Technology
文件頁(yè)數(shù): 27/40頁(yè)
文件大小: 0K
描述: MCU PIC 8BIT 4K FLASH 28SDIP
標(biāo)準(zhǔn)包裝: 15
系列: PIC® XLP™ 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 32MHz
連通性: I²C,LIN,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,LCD,POR,PWM,WDT
輸入/輸出數(shù): 25
程序存儲(chǔ)器容量: 7KB(4K x 14)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 11x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 28-DIP(0.300",7.62mm)
包裝: 管件
2008 Microchip Technology Inc.
Advance Information
DS41360A-page 33
PIC16F193X/LF193X
8.0
ELECTRICAL SPECIFICATIONS
Refer to device specific data sheet for absolute
maximum ratings.
TABLE 8-1:
AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE
AC/DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature
-40°C
≤ TA ≤ +85°C
Sym.
Characteristics
Min.
Typ.
Max.
Units
Conditions/Comments
Supply Voltages and currents
VDD
VDD
Read/Write and Row Erase
operations
PIC16F193X
2.1
5.5
V
PIC16LF193X
2.1
3.6
V
Bulk Erase operations
PIC16F193X
2.7
5.5
V
PIC16LF193X
2.7
3.6
V
IDDI
Current on VDD, Idle
1.0
mA
IDDP
Current on VDD, Programming
3.0
mA
IPP
VPP
Current on MCLR/VPP
600
μA
VIHH
High voltage on MCLR/VPP for
Program/Verify mode entry
8.0
9.0
V
TVHHR
MCLR rise time (VIL to VIHH) for
Program/Verify mode entry
——
1.0
μs
I/O pins
VIH
(ICSPCLK, ICSPDAT, MCLR/VPP) input high
level
0.8 VDD
——
V
VIL
(ICSPCLK, ICSPDAT, MCLR/VPP) input low level
0.2 VDD
V
VOH
ICSPDAT output high level
VDD-0.7
——
V
IOH = 3.5 mA, VDD = 5V
IOH = 3 mA, VDD = 3.3V
IOH = 2 mA, VDD = 1.8V
VOL
ICSPDAT output low level
——
VSS+0.6
V
IOH = 8 mA, VDD = 5V
IOH = 6 mA, VDD = 3.3V
IOH = 3 mA, VDD = 1.8V
Programming mode entry and exit
TENTS
Programing mode entry setup time: ICSPCLK,
ICSPDAT setup time before VDD or MCLR
100
ns
TENTH
Programing mode entry hold time: ICSPCLK,
ICSPDAT hold time after VDD or MCLR
250
μs
Serial Program/Verify
TCKL
Clock Low Pulse Width
100
ns
TCKH
Clock High Pulse Width
100
ns
TDS
Data in setup time before clock
100
ns
TDH
Data in hold time after clock
100
ns
TCO
Clock
↑ to data out valid (during a
Read Data command)
0
80
ns
TLZD
Clock
↓ to data low-impedance (during a
Read Data command)
0
80
ns
THZD
Clock
↓ to data high-impedance (during a
Read Data command)
0
80
ns
TDLY
Data input not driven to next clock input (delay
required between command/data or
command/command)
1.0
μs
TERAB
Bulk Erase cycle time
5
ms
TERAR
Row Erase cycle time
2.5
ms
TPINT
Internally timed programming operation time
2.5
5
ms
Program memory
Configuration words
TPEXT
Externally timed programming pulse
1.0
2.1
ms
TDIS
Time delay from program to compare
(HV discharge time)
100
μs
TEXIT
Time delay when exiting Program/Verify mode
1
μs
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