參數(shù)資料
型號(hào): PIC16LF1828-E/P
廠商: Microchip Technology
文件頁數(shù): 49/101頁
文件大?。?/td> 0K
描述: IC MCU 8BIT 7KB FLASH 20PDIP
標(biāo)準(zhǔn)包裝: 22
系列: PIC® XLP™ mTouch™ 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 32MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 17
程序存儲(chǔ)器容量: 7KB(4K x 14)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 20-DIP(0.300",7.62mm)
包裝: 管件
192
2552K–AVR–04/11
ATmega329/3290/649/6490
Bit 6 – TXCIEn: TX Complete Interrupt Enable
Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt
will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is
written to one and the TXCn bit in UCSRnA is set.
Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable
Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will
be generated only if the UDRIEn bit is written to one, the Global Interrupt Flag in SREG is written
to one and the UDREn bit in UCSRnA is set.
Bit 4 – RXEN0: Receiver Enable
Writing this bit to one enables the USART Receiver. The Receiver will override normal port oper-
ation for the RxD pin when enabled. Disabling the Receiver will flush the receive buffer
invalidating the FEn, DORn, and UPEn Flags.
Bit 3 – TXENn: Transmitter Enable
Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port
operation for the TxD pin when enabled. The disabling of the Transmitter (writing TXENn to
zero) will not become effective until ongoing and pending transmissions are completed, i.e.,
when the Transmit Shift Register and Transmit Buffer Register do not contain data to be trans-
mitted. When disabled, the Transmitter will no longer override the TxD port.
Bit 2 – UCSZn2: Character Size
The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRnC sets the number of data bits
(Character SiZe) in a frame the Receiver and Transmitter use.
Bit 1 – RXB8n: Receive Data Bit 8
RXB8n is the ninth data bit of the received character when operating with serial frames with nine
data bits. Must be read before reading the low bits from UDRn.
Bit 0 – TXB8n: Transmit Data Bit 8
TXB8n is the ninth data bit in the character to be transmitted when operating with serial frames
with nine data bits. Must be written before writing the low bits to UDRn.
19.11.4
UCSRnC – USART Control and Status Register n C
Bit 6 – UMSELn: USART Mode Select
This bit selects between asynchronous and synchronous mode of operation.
Bit
7
6
543
2
1
0
UMSELn
UPMn1
UPMn0
USBSn
UCSZn1
UCSZn0
UCPOLn
UCSRnC
Read/Write
R
R/W
Initial Value
0
1
0
Table 19-8.
UMSELn Bit Settings
UMSELn
Mode
0
Asynchronous Operation
1
Synchronous Operation
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