參數(shù)資料
型號: PIC16LF1827-I/ML
廠商: Microchip Technology
文件頁數(shù): 70/109頁
文件大小: 0K
描述: IC PIC MCU FLASH 4K 28-QFN
產(chǎn)品培訓(xùn)模塊: XLP Deep Sleep Mode
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 61
系列: PIC® XLP™ mTouch™ 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 32MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲器容量: 7KB(4K x 14)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 384 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-VQFN 裸露焊盤
包裝: 托盤
產(chǎn)品目錄頁面: 655 (CN2011-ZH PDF)
SC16C850
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 11 November 2010
23 of 55
NXP Semiconductors
SC16C850
2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
7.1 Transmit (THR) and Receive (RHR) Holding Registers
The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D7 to D0) to the
transmit FIFO. The THR empty flag in the LSR will be set to a logic 1 when the transmit
FIFO is empty or when data is transferred to the TSR.
The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a
Receive Serial Shift Register (RSR). Receive data is removed from the SC16C850
receive FIFO by reading the RHR. The receive section provides a mechanism to prevent
false starts. On the falling edge of a start or false start bit, an internal receiver counter
starts counting clocks at the 16
× clock rate. After 71
2 clocks, the start bit time should be
shifted to the center of the start bit. At this time the start bit is sampled, and if it is still a
logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from
assembling a false character. Receiver status codes will be posted in the LSR.
7.2 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter
empty, line status and modem status registers. These interrupts would normally be seen
on the INT output pin.
Table 9.
Interrupt Enable Register bits description
Bit
Symbol
Description
7
IER[7]
CTS interrupt.
logic 0 = disable the CTS interrupt (normal default condition)
logic 1 = enable the CTS interrupt. The SC16C850 issues an interrupt when
the CTS pin transitions from a logic 0 to a logic 1.
6
IER[6]
RTS interrupt.
logic 0 = disable the RTS interrupt (normal default condition)
logic 1 = enable the RTS interrupt. The SC16C850 issues an interrupt when
the RTS pin transitions from a logic 0 to a logic 1.
5
IER[5]
Xoff interrupt.
logic 0 = disable the software flow control, receive Xoff interrupt (normal default
condition)
logic 1 = enable the receive Xoff interrupt
4
IER[4]
Sleep mode.
logic 0 = disable Sleep mode (normal default condition)
logic 1 = enable Sleep mode
3
IER[3]
Modem Status Interrupt. This interrupt will be issued whenever there is a modem
status change as reflected in MSR[3:0].
logic 0 = disable the modem status register interrupt (normal default condition)
logic 1 = enable the modem status register interrupt
2
IER[2]
Receive Line Status interrupt. This interrupt will be issued whenever a receive
data error condition exists as reflected in LSR[4:1].
logic 0 = disable the receiver line status interrupt (normal default condition)
logic 1 = enable the receiver line status interrupt
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