參數(shù)資料
型號(hào): PIC16LF1827-I/ML
廠商: Microchip Technology
文件頁數(shù): 69/109頁
文件大小: 0K
描述: IC PIC MCU FLASH 4K 28-QFN
產(chǎn)品培訓(xùn)模塊: XLP Deep Sleep Mode
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 61
系列: PIC® XLP™ mTouch™ 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 32MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲(chǔ)器容量: 7KB(4K x 14)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 384 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-VQFN 裸露焊盤
包裝: 托盤
產(chǎn)品目錄頁面: 655 (CN2011-ZH PDF)
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SC1
6
C850
Al
li
n
for
m
at
ion
pr
ovi
ded
in
this
do
cum
ent
i
s
sub
jec
tto
leg
a
ld
is
c
la
im
er
s.
NXP
B.V
.
2010.
Al
lr
ig
h
ts
re
s
e
rv
ed.
Produ
ct
d
a
ta
sheet
R
e
v
.2
1
N
o
vem
ber
2010
22
o
f55
N
X
P
Semi
conductor
s
SC16C850
2
.5
to
3.3
V
UART
with
1
28-
byt
e
FIFOs
and
IrDA
e
n
cod
e
r/dec
ode
r
[1]
The value shown represents the register’s initialized HEX value; X = not applicable.
[2]
Accessible only when LCR[7] is logic 0, and EFCR[2:0] are logic 000b.
[3]
This bit is only accessible when EFR[4] is set.
[4]
Baud rate registers accessible only when LCR[7] is logic 1.
[5]
Enhanced Feature Register, Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to 0xBF, and EFCR[2:1] are logic 0.
[6]
Second Special registers are accessible only when EFCR[0] = 1, and EFCR[2:1] are logic 0.
[7]
First extra feature register set is only accessible when EFCR[2:1] = 01b.
[8]
Second extra feature register set is only accessible when EFCR[2:1] = 10b.
Enhanced feature register set[5]
0
1
0
EFR
0x00
Auto CTS
Auto RTS
special
character
select
Enable
IER[7:4],
ISR[5:4],
FCR[5:4],
MCR[7:5]
Cont-3 TX,
RX Control
Cont-2 TX,
RX Control
Cont-1 TX,
RX Control
Cont-0 TX,
RX Control
R/W
1
0
Xon1
0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
1
0
1
Xon2
0x00
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
R/W
1
0
Xoff1
0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
1
Xoff2
0x00
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
R/W
First extra feature register set[7]
0
1
0
TXINTLVL
0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
1
0
RXINTLVL
0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
1
0
FLWCNTH
0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
1
FLWCNTL
0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
Second extra feature register set[8]
0
1
0
CLKPRES
0x00
reserved
bit 3
bit 2
bit 1
bit 0
R/W
1
0
RS485TIME 0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
1
0
AFCR2
0x00
reserved
RS485 RTS
Invert
Auto RS485
RTS
RS485
RTS/DTR
Transmitter
Disable
Receiver
Disable
9-bit Enable
R/W
1
AFCR1
0x00
reserved
Sleep
RXLow
reserved
RTS/CTS
mapped to
DTR/DSR
Software
Reset
TSR
Interrupt
R/W
Table 8.
SC16C850 internal registers …continued
A2 A1 A0 Register
Default[1]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
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