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參數資料
| 型號： | PIC16LF1508-E/P |
| 廠商： | Microchip Technology |
| 文件頁數： | 46/123頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8BIT 7KB FLASH 20-PDIP |
| 標準包裝： | 22 |
| 系列： | PIC® XLP™ 16F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | I²C，LIN，SPI，UART/USART |
| 外圍設備： | 欠壓檢測/復位，POR，PWM，WDT |
| 輸入/輸出數： | 17 |
| 程序存儲器容量： | 7KB（4K x 14） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.8 V ~ 3.6 V |
| 數據轉換器： | A/D 12x10b，D/A 1x5b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 包裝： | 管件 |
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Micrel, Inc.
KSZ8873MLLJ
September 2011
29
M9999-091911-1.8
The MII operates in either PHY mode or MAC mode. The data interface is a nibble wide and runs at the network bit rate
(not encoded). Additional signals on the transmit side indicate when data is valid or when an error occurs during
transmission. Similarly, the receive side has signals that convey when the data is valid and without physical layer errors.
For half duplex operation, the SCOL signal indicates if a collision has occurred during transmission.
The KSZ8873MLLJ does not provide the MRXER signal for PHY mode operation and the MTXER signal for MAC mode
operation. Normally, MRXER indicates a receive error coming from the physical layer device and MTXER indicates a
transmit error from the MAC device. Since the switch filters error frames, these MII error signals are not used by the
KSZ8873MLLJ. So, for PHY mode operation, if the device interfacing with the KSZ8873MLLJ has an MRXER input pin, it
needs to be tied low. And, for MAC mode operation, if the device interfacing with the KSZ8873 MLLJ has an MTXER input
pin, it also needs to be tied low.
The KSZ8873MLLJ provides a bypass feature in the MII PHY mode. Pin SMTXER3/MII_LINK is used for MII link status. If
the host is power down, pin MII_LINK will go to high. In this case, no new ingress frames from port1 or port 2 will be sent
out through port 3, and the frames for port 3 already in packet memory will be flushed out.
MII Management (MIIM) Interface
The KSZ8873MLLJ supports the IEEE 802.3 MII Management Interface, also known as the Management Data
Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the states of the
KSZ8873MLLJ. An external device with MDC/MDIO capability is used to read the PHY status or configure the PHY
settings. Further detail on the MIIM interface is found in Clause 22.2.4.5 of the IEEE 802.3u Specification and refer to
802.3 section 22.3.4 for the timing.
The MIIM interface consists of the following:
A physical connection that incorporates the data line (SDA_MDIO) and the clock line (SCL_MDC).
A specific protocol that operates across the aforementioned physical connection that allows an external
controller to communicate with the KSZ8873MLLJ device.
Access to a set of eight 16-bit registers, consisting of six standard MIIM registers [0:5] and two custom MIIM
registers [29, 31].
The MIIM Interface can operate up to a maximum clock speed of 5MHz.
The following table depicts the MII Management Interface frame format.
Preamble
Start of
Frame
Read/Write
OP Code
PHY
Address
Bits [4:0]
REG
Address
Bits [4:0]
TA
Data Bits [15:0]
Idle
Read
32 1’s
01
10
AAAAA
RRRRR
Z0
DDDDDDDD_DDDDDDDD
Z
Write
32 1’s
01
AAAAA
RRRRR
10
DDDDDDDD_DDDDDDDD
Z
Table 4. MII Management Interface Frame Format
Serial Management Interface (SMI)
The SMI is the KSZ8873MLLJ non-standard MIIM interface that provides access to all KSZ8873MLLJ configuration
registers. This interface allows an external device to completely monitor and control the states of the KSZ8873MLLJ.
The SMI interface consists of the following:
A physical connection that incorporates the data line (SDA_MDIO) and the clock line (SCL_MDC).
A specific protocol that operates across the aforementioned physical connection that allows an external
controller to communicate with the KSZ8873MLLJ device.
Access to all KSZ8873MLLJ configuration registers. Register access includes the Global, Port and Advanced
Control Registers 0-198 (0x00 – 0xC6), and indirect access to the standard MIIM registers [0:5] and custom
MIIM registers [29, 31].
The following table depicts the SMI frame format.
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