參數(shù)資料
型號(hào): PIC16LCE623-04E/P
廠商: Microchip Technology
文件頁數(shù): 61/100頁
文件大?。?/td> 0K
描述: IC MCU CMOS.5K OTP W/EEPRM 18DIP
標(biāo)準(zhǔn)包裝: 25
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 4MHz
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,WDT
輸入/輸出數(shù): 13
程序存儲(chǔ)器容量: 896B(512 x 14)
程序存儲(chǔ)器類型: OTP
EEPROM 大小: 128 x 8
RAM 容量: 96 x 8
電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
振蕩器型: 外部
工作溫度: -40°C ~ 125°C
封裝/外殼: 18-DIP(0.300",7.62mm)
包裝: 管件
1999 Microchip Technology Inc.
DS40182C-page 53
PIC16CE62X
10.3
Reset
The PIC16CE62X differentiates between various kinds
of reset:
a)
Power-on reset (POR)
b)
MCLR reset during normal operation
c)
MCLR reset during SLEEP
d)
WDT reset (normal operation)
e)
WDT wake-up (SLEEP)
f)
Brown-out Reset (BOD)
Some registers are not affected in any reset condition.
Their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset
state” on Power-on reset, MCLR reset, WDT reset and
MCLR reset during SLEEP. They are not affected by a
WDT wake-up, since this is viewed as the resumption
of normal operation. TO and PD bits are set or cleared
differently in different reset situations as indicated in
Table 10-4. These bits are used in software to deter-
mine the nature of the reset. See Table 10-6 for a full
description of reset states of all registers.
A simplified block diagram of the on-chip reset circuit is
shown in Figure 10-6.
The MCLR reset path has a noise filter to detect and
ignore small pulses. See Table 13-5 for pulse width
specification.
FIGURE 10-6: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
R
Q
External
Reset
MCLR/
VDD
OSC1/
WDT
Module
VDD rise
detect
OST/PWRT
On-chip(1)
RC OSC
WDT
Time-out
Power-on Reset
OST
PWRT
Chip_Reset
10-bit Ripple-counter
Reset
Enable OST
Enable PWRT
SLEEP
See Table 10-3 for time-out situations.
Note 1:
This is a separate oscillator from the RC oscillator of the CLKIN pin.
Brown-out
Reset
BODEN
CLKIN
Pin
VPP Pin
10-bit Ripple-counter
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