2002 Microchip Technology Inc.
DS41120B-page 177
PIC16C717/770/771
15.6
Master SSP I2C Mode Timing Waveforms and Requirements
FIGURE 15-22:
MASTER SSP I2C BUS START/STOP BITS TIMING WAVEFORMS
TABLE 15-21: MASTER SSP I2C BUS START/STOP BITS REQUIREMENTS
FIGURE 15-23:
MASTER SSP I2C BUS DATA TIMING
Param.
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
90*
TSU:STA
START condition
100 kHz mode
2(TOSC)(BRG + 1)
——
ns
Only relevant for a Repeated
START
condition
Setup time
400 kHz mode
2(TOSC)(BRG + 1)
——
1 MHz mode(1)
2(TOSC)(BRG + 1)
——
91*
THD:STA
START condition
100 kHz mode
2(TOSC)(BRG + 1)
——
ns
After this period the first clock
pulse is generated
Hold time
400 kHz mode
2(TOSC)(BRG + 1)
——
1 MHz mode(1)
2(TOSC)(BRG + 1)
——
92*
TSU:STO
STOP condition
100 kHz mode
2(TOSC)(BRG + 1)
——
ns
Setup time
400 kHz mode
2(TOSC)(BRG + 1)
——
1 MHz mode(1)
2(TOSC)(BRG + 1)
——
93*
THD:STO
STOP condition
100 kHz mode
2(TOSC)(BRG + 1)
——
ns
Hold time
400 kHz mode
2(TOSC)(BRG + 1)
——
1 MHz mode(1)
2(TOSC)(BRG + 1)
——
*
These parameters are characterized but not tested. For the value required by the I2C specification, please refer to the PICmi-
croTM Mid-Range MCU Family Reference Manual (DS33023).
Maximum pin capacitance = 10 pF for all I2C pins.
91
93
SCL
SDA
START
Condition
STOP
Condition
90
92
90
91
92
100
101
103
106
107
109
110
102
SCL
SDA
In
SDA
Out