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鍨嬭櫉(h脿o)锛� PIC16F87T-I/SS
寤犲晢锛� Microchip Technology
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 97/200闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC MCU FLASH 4KX14 EEPROM 20SSOP
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鏍稿績铏曠悊鍣細 PIC
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杓稿叆/杓稿嚭鏁�(sh霉)锛� 16
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RAM 瀹归噺锛� 368 x 8
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鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
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鍖呰锛� 甯跺嵎 (TR)
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186
8008H鈥揂VR鈥�04/11
ATtiny48/88
19.1.3
Preventing Flash Corruption
During periods of low V
CC, the Flash program can be corrupted because the supply voltage is
too low for the CPU and the Flash to operate properly. These issues are the same as for board
level systems using the Flash, and the same design solutions should be applied.
A Flash program corruption can be caused by two situations when the voltage is too low. First, a
regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,
the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions
is too low.
Flash corruption can easily be avoided by following these design recommendations (one is
sufficient):
1.
Keep the AVR RESET active (low) during periods of insufficient power supply voltage.
This can be done by enabling the internal Brown-out Detector (BOD) if the operating
voltage matches the detection level. If not, an external low V
CC reset protection circuit
can be used. If a reset occurs while a write operation is in progress, the write operation
will be completed provided that the power supply voltage is sufficient.
2.
Keep the AVR core in Power-down sleep mode during periods of low V
CC. This will pre-
vent the CPU from attempting to decode and execute instructions, effectively protecting
the SPMCSR Register and thus the Flash from unintentional writes.
19.1.4
Programming Time for Flash when Using SPM
The calibrated oscillator is used to time Flash accesses. Table 19-1 shows the typical program-
ming time for Flash accesses from the CPU.
19.2
Register Description
19.2.1
SPMCSR 鈥� Store Program Memory Control and Status Register
The Store Program Memory Control and Status Register contains the control bits needed to con-
trol the Program memory operations.
Bit 7 鈥� Res: Reserved Bit
This bit is reserved and will always read zero.
Bit 6 鈥� RWWSB: Read-While-Write Section Busy
This bit is for compatibility with devices supporting Read-While-Write. It will always read as zero
in ATtiny48/88.
Table 19-1.
SPM Programming Time
Symbol
Min Programming Time
Max Programming Time
Flash write (Page Erase, Page Write, and
write Lock bits by SPM)
3.7 ms
4.5 ms
Bit
7
6
5
4
3
2
1
0
鈥�
RWWSB
鈥�
CTPB
RFLB
PGWRT
PGERS
SELFPRGEN
SPMCSR
Read/Write
R
R/W
Initial Value
0
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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