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參數(shù)資料
| 型號： | PIC16F77T-I/ML |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 43/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU FLASH 8KX14 A/D 44QFN |
| 標(biāo)準(zhǔn)包裝： | 1,600 |
| 系列： | PIC® 16F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 33 |
| 程序存儲器容量： | 14KB（8K x 14） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 368 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x8b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-VQFN 裸露焊盤 |
| 包裝： | 帶卷 (TR) |
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2002 Microchip Technology Inc.
DS30325B-page 33
PIC16F7X
4.2
PORTB and the TRISB Register
PORTB is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= ‘1’) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISB bit (= ‘0’) will
make the corresponding PORTB pin an output (i.e., put
the contents of the output latch on the selected pin).
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (OPTION_REG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are dis-
abled on a Power-on Reset.
FIGURE 4-3:
BLOCK DIAGRAM OF
RB3:RB0 PINS
Four of the PORTB pins (RB7:RB4) have an inter-
rupt-on-change feature. Only pins configured as inputs
can cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the inter-
rupt-on-change comparison). The input pins (of
RB7:RB4) are compared with the old value latched on
the last read of PORTB. The “mismatch” outputs of
RB7:RB4 are ORed together to generate the RB Port
Change Interrupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
Any read or write of PORTB. This will end the
mismatch condition.
b)
Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
This interrupt on mismatch feature, together with soft-
ware configureable pull-ups on these four pins, allow
easy interface to a keypad and make it possible for
wake-up on key depression. Refer to the Embedded
Control Handbook, “Implementing Wake-up on Key
Stroke” (AN552).
RB0/INT is an external interrupt input pin and is config-
ured using the INTEDG bit (OPTION_REG<6>).
RB0/INT is discussed in detail in Section 12.11.1.
FIGURE 4-4:
BLOCK DIAGRAM OF
RB7:RB4 PINS
Data Latch
RBPU(2)
P
VDD
Q
D
CK
Q
D
CK
QD
EN
Data Bus
WR Port
WR TRIS
RD TRIS
RD Port
Weak
Pull-up
RD Port
RB0/INT
I/O
pin(1)
TTL
Input
Buffer
Schmitt Trigger
Buffer
TRIS Latch
Note 1:
I/O pins have diode protection to VDD and VSS.
2:
To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION_REG<7>).
Data Latch
From other
RBPU(2)
P
VDD
I/O
Q
D
CK
Q
D
CK
QD
EN
QD
EN
Data Bus
WR Port
WR TRIS
Set RBIF
TRIS Latch
RD TRIS
RD Port
RB7:RB4 pins
Weak
Pull-up
RD Port
Latch
TTL
Input
Buffer
pin(1)
ST
Buffer
RB7:RB6 in Serial Programming mode
Q3
Q1
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
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