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參數(shù)資料
| 型號(hào)： | PIC16F74T-I/ML |
| 廠商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 69/104頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU FLASH 4KX14 A/D 44QFN |
| 標(biāo)準(zhǔn)包裝： | 1,600 |
| 系列： | PIC® 16F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 33 |
| 程序存儲(chǔ)器容量： | 7KB（4K x 14） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 192 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x8b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-VQFN 裸露焊盤 |
| 包裝： | 帶卷 (TR) |
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Micrel, Inc.
KSZ8851-16MLLJ
March 2010
59
M9999-030210-1.0
Receive Frame Header Status Register (0x7C – 0x7D): RXFHSR (Continued)
2
-
RO
RXFTL Receive Frame Too Long
When this bit is set, it indicates that the frame length exceeds the maximum size of 2000
bytes. Frames that are too long are passed to the host only if the pass bad frame bit is set.
Note: Frame too long is only a frame length indication and does not cause any frame
truncation.
1
-
RO
RXRF Receive Runt Frame
When this bit is set, it indicates that a frame was damaged by a collision or had a
premature termination before the collision window passed.
Runt frames are passed to the host only if the pass bad frame bit is set.
0
-
RO
RXCE Receive CRC Error
When this bit is set, it indicates that a CRC error has occurred on the current received
frame.
CRC error frames are passed to the host only if the pass bad frame bit is set.
Receive Frame Header Byte Count Register (0x7E – 0x7F): RXFHBCR
This register indicates the received frame header byte count information, the received frames are reported in RXFCTR
register. This register contains the total number of bytes information for the frame received and the CPU can read so
many times same as the frame count value in the RXFCTR.
Bit
Default Value
R/W
Description
15-12
-
RO
Reserved.
11-0
-
RO
RXBC Receive Byte Count
This field indicates the present received frame byte size.
Note: Always read low byte first for 8-bit mode opearation.
TXQ Command Register (0x80 – 0x81): TXQCR
This register is programmed by the Host CPU to issue a transmit command to the TXQ. The present transmit frame in
the TXQ memory is queued for transmit.
Bit
Default Value
R/W
Description
15-3
-
RW
Reserved
2
0x0
RW
AETFE Auto-Enqueue TXQ Frame Enable
When this bit is written as 1, the KSZ8851-16MLLJ will enable current all TX frames
prepared in the TX buffer are queued to transmit automatically.
The bit 0 METFE has to be set 0 when this bit is set to 1 in this register.
1
0x0
RW
TXQMAM TXQ Memory Available Monitor
When this bit is written as 1, the KSZ8851-16MLLJ will generate interrupt (bit 6 in ISR
register) to CPU when TXQ memory is available based upon the total amount of TXQ
space requested by CPU at TXNTFSR (0x9E) register.
Note: This bit is self-clearing after the frame is finished transmitting. The software should
wait for the bit to be cleared before set to 1 again.
0
0x0
RW
METFE Manual Enqueue TXQ Frame Enable
When this bit is written as 1, the KSZ8851-16MLLJ will enable current TX frame prepared
in the TX buffer is queued for transmit, this is only transmit one frame at a time.
Note: This bit is self-clearing after the frame is finished transmitting. The software should
wait for the bit to be cleared before setting up another new TX frame.
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