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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | PIC16F72-E/ML |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 24/136闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC PIC MCU FLASH 2KX14 28QFN |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Asynchronous Stimulus |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 61 |
| 绯诲垪锛� | PIC® 16F |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 20MHz |
| 閫ｉ€氭€э細 | I²C锛孲PI |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯/寰�(f霉)浣嶏紝POR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 22 |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 | 3.5KB锛�2K x 14锛� |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 | 闁冨瓨 |
| RAM 瀹归噺锛� | 128 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 4 V ~ 5.5 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 5x8b |
| 鎸暕鍣ㄥ瀷锛� | 澶栭儴 |
| 宸ヤ綔婧害锛� | -40°C ~ 125°C |
| 灏佽/澶栨锛� | 28-VQFN 瑁搁湶鐒婄洡 |
| 鍖呰锛� | 绠′欢 |
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PIC16F72
DS39597C-page 10
2007 Microchip Technology Inc.
Bank 1
80h(1)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000
81h
OPTION
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
82h(1)
PCL
Program Counter's (PC) Least Significant Byte
0000 0000
83h(1)
STATUS
IRP
RP1
RP0
TO
PD
ZDC
C
0001 1xxx
84h(1)
FSR
Indirect Data Memory Address Pointer
xxxx xxxx
85h
TRISA
鈥�
PORTA Data Direction Register
--11 1111
86h
TRISB
PORTB Data Direction Register
1111 1111
87h
TRISC
PORTC Data Direction Register
1111 1111
88h
鈥�
Unimplemented
鈥�
89h
鈥�
Unimplemented
鈥�
8Ah(1,2)
PCLATH
鈥�
Write Buffer for the upper 5 bits of the PC
---0 0000
8Bh(1)
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
8Ch
PIE1
鈥擜DIE
鈥�
SSPIE
CCP1IE
TMR2IE
TMR1IE
-0-- 0000
8Dh
鈥�
Unimplemented
鈥�
8Eh
PCON
鈥�
鈥擯OR
BOR
---- --qq
8Fh
鈥�
Unimplemented
鈥�
90h
鈥�
Unimplemented
鈥�
91h
鈥�
Unimplemented
鈥�
92h
PR2
Timer2 Period Register
1111 1111
93h
SSPADD
Synchronous Serial Port (I2C mode) Address Register
0000 0000
94h
SSPSTAT
SMP
CKE
D/A
PS
R/W
UA
BF
0000 0000
95h
鈥�
Unimplemented
鈥�
96h
鈥�
Unimplemented
鈥�
97h
鈥�
Unimplemented
鈥�
98h
鈥�
Unimplemented
鈥�
99h
鈥�
Unimplemented
鈥�
9Ah
鈥�
Unimplemented
鈥�
9Bh
鈥�
Unimplemented
鈥�
9Ch
鈥�
Unimplemented
鈥�
9Dh
鈥�
Unimplemented
鈥�
9Eh
鈥�
Unimplemented
鈥�
9Fh
ADCON1
鈥�
PCFG2
PCFG1
PCFG0
---- -000
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details on
page:
Legend:
x
= unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as 鈥�0鈥�, r = reserved.
Shaded locations are unimplemented, read as 鈥�0鈥�.
Note
1:
These registers can be addressed from any bank.
2:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
3:
This bit always reads as a 鈥�1鈥�.
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