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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | PIC16F72-E/ML |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 103/136闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC PIC MCU FLASH 2KX14 28QFN |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Asynchronous Stimulus |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 61 |
| 绯诲垪锛� | PIC® 16F |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 20MHz |
| 閫ｉ€氭€э細 | I²C锛孲PI |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯/寰�(f霉)浣嶏紝POR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 22 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 3.5KB锛�2K x 14锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | 闁冨瓨 |
| RAM 瀹归噺锛� | 128 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 4 V ~ 5.5 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 5x8b |
| 鎸暕鍣ㄥ瀷锛� | 澶栭儴 |
| 宸ヤ綔婧害锛� | -40°C ~ 125°C |
| 灏佽/澶栨锛� | 28-VQFN 瑁搁湶鐒婄洡 |
| 鍖呰锛� | 绠′欢 |
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69
2535J鈥揂VR鈥�08/10
ATtiny13
Figure 11-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-
caler (fclk_I/O/8)
11.9 Register Description
11.9.1
TCCR0A 鈥� Timer/Counter Control Register A
Bits 7:6 鈥� COM01A:0: Compare Match Output A Mode
These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0
bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin
must be set in order to enable the output driver.
When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the
WGM02:0 bit setting.
Table 11-2 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to a normal or
CTC mode (non-PWM).
Table 11-3 on page 70 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to
fast PWM mode.
OCFnx
OCRnx
TCNTn
(CTC)
TOP
TOP - 1
TOP
BOTTOM
BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O/8)
Bit
7
6
5
4
3
210
COM0A1
COM0A0
COM0B1
COM0B0
鈥�
WGM01
WGM00
TCCR0A
Read/Write
R/W
R
R/W
Initial Value
0
Table 11-2.
Compare Output Mode, non-PWM Mode
COM01
COM00
Description
0
Normal port operation, OC0A disconnected.
0
1
Toggle OC0A on Compare Match
1
0
Clear OC0A on Compare Match
1
Set OC0A on Compare Match
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