PIC16F627A/628A/648A
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� PIC16F628AT-I/SS
寤犲晢锛� Microchip Technology
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EEPROM 澶у皬锛� 128 x 8
RAM 瀹归噺锛� 224 x 8
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鍖呰锛� 甯跺嵎 (TR)
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AC162053-ND - HEADER INTERFACE ICD,ICD2 18DIP
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PIC16F627A/628A/648A
DS40044G-page 140
2009 Microchip Technology Inc.
17.4
DC Characteristics:
PIC16F627A/628A/648A (Industrial, Extended)
PIC16LF627A/628A/648A (Industrial)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40掳C
鈮� TA 鈮� +85掳C for industrial and
-40掳C
鈮� TA 鈮� +125掳C for extended
Operating voltage VDD range as described in DC specification Table 17-2 and
Param.
No.
Sym
Characteristic/Device
Min
Typ
Max
Unit
Conditions
VIL
Input Low Voltage
D030
D031
D032
D033
I/O ports
with TTL buffer
with Schmitt Trigger input(4)
MCLR, RA4/T0CKI,OSC1
(in RC mode)
OSC1 (in HS)
OSC1 (in LP and XT)
VSS
鈥�
0.8
0.15 VDD
0.2 VDD
0.3 VDD
0.6
V
VDD = 4.5V to 5.5V
otherwise
(Note1)
VIH
Input High Voltage
D040
D041
D042
D043
D043A
D043B
I/O ports
with TTL buffer
with Schmitt Trigger input(4)
MCLR RA4/T0CKI
OSC1 (XT and LP)
OSC1 (in RC mode)
OSC1 (in HS mode)
2.0V
.25 VDD + 0.8V
0.8 VDD
1.3
0.9 VDD
0.7 VDD
鈥�
VDD
V
VDD = 4.5V to 5.5V
otherwise
(Note1)
D070
IPURB
PORTB weak pull-up
current
50
200
400
渭AVDD = 5.0V, VPIN = VSS
IIL
Input Leakage Current(2), (3)
D060
D061
D063
I/O ports (Except PORTA)
PORTA(4)
RA4/T0CKI
OSC1, MCLR
鈥�
卤1.0
卤0.5
卤1.0
卤5.0
渭A
VSS
鈮� VPIN 鈮� VDD, pin at high-impedance
VSS
鈮� VPIN 鈮� VDD, pin at high-impedance
VSS
鈮� VPIN 鈮� VDD
VSS
鈮� VPIN 鈮� VDD, XT, HS and LP
oscillator configuration
VOL
Output Low Voltage
D080
I/O ports(4)
鈥�
0.6
V
IOL = 8.5 mA, VDD = 4.5 V, -40
掳 to +85掳C
IOL = 7.0 mA, VDD = 4.5 V, +85
掳 to
+125
掳C
VOH
Output High Voltage(3)
D090
I/O ports (Except RA4(4) )VDD 鈥� 0.7
VDD 鈥� 0.7
鈥�
V
IOH = -3.0 mA, VDD = 4.5 V, -40
掳 to +85掳C
IOH = -2.5 mA, VDD = 4.5 V, +85
掳 to
+125
掳C
D150
VOD
Open-Drain High Voltage
鈥�
8.5*
V
RA4 pin PIC16F627A/628A/648A,
PIC16LF627A/628A/648A
Capacitive Loading Specs on Output Pins
D100*
D101*
COSC2
CIO
OSC2 pin
All I/O pins/OSC2 (in RC mode)
鈥�
15
50
pF
In XT, HS and LP modes when external
clock used to drive OSC1.
*
These parameters are characterized but not tested.
Data in 鈥淭yp鈥� column is at 5.0V, 25
掳C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note
1:
In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the PIC16F627A/628A/648A
be driven with external clock in RC mode.
2:
The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent normal
operating conditions. Higher leakage current may be measured at different input voltages.
3:
Negative current is defined as coming out of the pin.
4:
Includes OSC1 and OSC2 when configured as I/O pins, CLKIN or CLKOUT.
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PIC16F628T-04/SO 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 3.5KB 224 RAM 16 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT
PIC16F628T-04/SS 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 3.5KB 224 RAM 16 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT
PIC16F628T-04E/SO 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 3.5KB 224 RAM 16 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT
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PIC16F628T-04I/SO 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 3.5KB 224 RAM 16 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT
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