
2009 Microchip Technology Inc.
DS40044G-page 27
PIC16F627A/628A/648A
4.2.2.4
PIE1 Register
This register contains interrupt enable bits.
REGISTER 4-4:
PIE1 – PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch)
R/W-0
U-0
R/W-0
EEIE
CMIE
RCIE
TXIE
—
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 0
bit 7
EEIE:
EE Write Complete Interrupt Enable Bit
1
= Enables the EE write complete interrupt
0
= Disables the EE write complete interrupt
bit 6
CMIE
: Comparator Interrupt Enable bit
1
= Enables the comparator interrupt
0
= Disables the comparator interrupt
bit 5
RCIE
: USART Receive Interrupt Enable bit
1
= Enables the USART receive interrupt
0
= Disables the USART receive interrupt
bit 4
TXIE
: USART Transmit Interrupt Enable bit
1
= Enables the USART transmit interrupt
0
= Disables the USART transmit interrupt
bit 3
Unimplemented
: Read as ‘0’
bit 2
CCP1IE
: CCP1 Interrupt Enable bit
1
= Enables the CCP1 interrupt
0
= Disables the CCP1 interrupt
bit 1
TMR2IE
: TMR2 to PR2 Match Interrupt Enable bit
1
= Enables the TMR2 to PR2 match interrupt
0
= Disables the TMR2 to PR2 match interrupt
bit 0
TMR1IE
: TMR1 Overflow Interrupt Enable bit
1
= Enables the TMR1 overflow interrupt
0
= Disables the TMR1 overflow interrupt
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown