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參數(shù)資料
| 型號： | PIC16F54T-I/SS |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 29/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU FLASH 512X12 20SSOP |
| 產(chǎn)品培訓模塊： | Asynchronous Stimulus |
| 標準包裝： | 1,600 |
| 系列： | PIC® 16F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 外圍設備： | POR，WDT |
| 輸入/輸出數(shù)： | 12 |
| 程序存儲器容量： | 768B（512 x 12） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 25 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 5.5 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 包裝： | 帶卷 (TR) |
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2007 Microchip Technology Inc.
DS41213D-page 33
PIC16F5X
7.0
TIMER0 MODULE AND TMR0
REGISTER
The Timer0 module has the following features:
8-bit Timer/Counter register, TMR0
- Readable and writable
8-bit software programmable prescaler
Internal or external clock select
- Edge select for external clock
Figure 7-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In Timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two cycles (Figure 7-2 and Figure 7-3).
The user can work around this by writing an adjusted
value to the TMR0 register.
Counter mode is selected by setting the T0CS bit
(OPTION<5>). In this mode, Timer0 will increment
either on every rising or falling edge of pin T0CKI. The
incrementing edge is determined by the source edge
select bit T0SE (OPTION<4>). Clearing the T0SE bit
selects the rising edge. Restrictions on the external
clock input are discussed in detail in Section 7.1
The prescaler assignment is controlled in software by
the control bit PSA (OPTION<3>). Clearing the PSA bit
will assign the prescaler to Timer0. The prescaler is not
readable or writable. When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4,...,
1:256 are selectable. Section 7.2 “Prescaler” details
the operation of the prescaler.
A summary of registers associated with the Timer0
module is found in Table 7-1.
FIGURE 7-1:
TIMER0 BLOCK DIAGRAM
FIGURE 7-2:
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALER
Note:
The prescaler may be used by either the
Timer0 module or the Watchdog Timer, but
not both.
Note 1:
Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in Section 3.4 “Option Register”.
2:
The prescaler is shared with the Watchdog Timer (Figure 7-5).
T0CKI
T0SE(1)
0
1
0
pin
T0CS(1)
FOSC/4
Programmable
Prescaler(2)
Sync with
Internal
Clocks
TMR0 Reg
PSout
(2 cycle delay)
PSout
Data Bus
8
PSA(1)
PS2, PS1, PS0(1)
3
Sync
PC - 1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
Instruction
Fetch
Timer0
PC
PC + 1
PC + 2
PC + 3
PC + 4
PC + 5
PC + 6
T0
T0 + 1
T0 + 2
NT0
NT0 + 1
NT0 + 2
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0 + 2
Instruction
Executed
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