參數(shù)資料
型號(hào)： PIC16F54T-I/SO
廠商： Microchip Technology
文件頁數(shù)： 27/88頁
文件大?。?/td> 0K
描述： IC MCU FLASH 512X12 18SOIC
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
標(biāo)準(zhǔn)包裝： 1,100
系列： PIC® 16F
核心處理器： PIC
芯體尺寸： 8-位
速度： 20MHz
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 12
程序存儲(chǔ)器容量： 768B（512 x 12）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 25 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 18-SOIC（0.295"，7.50mm 寬）
包裝： 帶卷 (TR)
2007 Microchip Technology Inc.
DS41213D-page 31
PIC16F5X
6.8
I/O Programming Considerations
6.8.1
BIDIRECTIONAL I/O PORTS
Some instructions operate internally as read followed
by write operations. The BCF and BSF instructions, for
example, read the entire port into the CPU, execute the
bit operation and re-write the result. Caution must be
used when these instructions are applied to a port
where one or more pins are used as input/outputs. For
example, a BSF operation on bit 5 of PORTB will cause
all eight bits of PORTB to be read into the CPU, bit 5 to
be set and the PORTB value to be written to the output
latches. If another bit of PORTB is used as a
bidirectional I/O pin (say bit ‘0’), and it is defined as an
input at this time, the input signal present on the pin
itself would be read into the CPU and rewritten to the
data latch of this particular pin, overwriting the previous
content. As long as the pin stays in the Input mode, no
problem occurs. However, if bit ‘0’ is switched into
Output mode later on, the content of the data latch may
now be unknown.
Example 6-1 shows the effect of two sequential read-
modify-write instructions (e.g., BCF, BSF, etc.) on an
I/O port.
A pin actively outputting a high or a low should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output currents may damage the
chip.
EXAMPLE 6-1:
READ-MODIFY-WRITE
INSTRUCTIONS ON AN I/O
PORT
6.8.2
SUCCESSIVE OPERATIONS ON I/O
PORTS
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle (see
Figure 6-2). Therefore, care must be exercised if a write
followed by a read operation is carried out on the same
I/O port. The sequence of instructions should allow the pin
voltage to stabilize (load dependent) before the next
instruction, which causes that file to be read into the CPU,
is executed. Otherwise, the previous state of that pin may
be read into the CPU rather than the new state. When in
doubt, it is better to separate these instructions with a NOP
or another instruction not accessing this I/O port.
FIGURE 6-2:
SUCCESSIVE I/O OPERATION
;Initial PORT Settings
;PORTB<7:4> Inputs
;PORTB<3:0> Outputs
;PORTB<7:6> have external pull-ups and are
;not connected to other circuitry
;
PORT latch PORT pins
;
----------- ----------
BCF
PORTB, 7
;01pp pppp
11pp pppp
BCF
PORTB, 6
;10pp pppp
11pp pppp
MOVLW H'3F'
;
TRIS
PORTB
;10pp pppp
10pp pppp
;
;Note that the user may have expected the
pin
;values to be 00pp pppp. The 2nd BCF caused
;RB7 to be latched as the pin value (High).
PC
PC + 1
PC + 2
PC + 3
Q1 Q2 Q3 Q4
Instruction
fetched
RB<7:0>
MOVWF PORTB
NOP
Port pin
sampled here
NOP
MOVF PORTB,W
Instruction
executed
MOVWF PORTB
(Write to
PORTB)
NOP
MOVF PORTB,W
This example shows a write
to PORTB followed by a read
from PORTB.
(Read
PORTB)
Port pin
written here
Fetch INST (PC)
Execute INST (PC - 1) Fetch INST (PC + 1)
Execute INST (PC)
Fetch INST (PC + 2)
Execute INST (PC + 1) Fetch INST (PC + 3)
Execute INST (PC + 2)
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