參數(shù)資料
型號(hào): PIC16F1827-I/ML
廠商: Microchip Technology
文件頁(yè)數(shù): 79/109頁(yè)
文件大小: 0K
描述: IC PIC MCU FLASH 4K 28-QFN
產(chǎn)品培訓(xùn)模塊: XLP Deep Sleep Mode
8-bit PIC® Microcontroller Portfolio
特色產(chǎn)品: Extreme Low Power (XLP) Microcontrollers
標(biāo)準(zhǔn)包裝: 61
系列: PIC® XLP™ mTouch™ 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 32MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲(chǔ)器容量: 7KB(4K x 14)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 384 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-VQFN 裸露焊盤(pán)
包裝: 托盤(pán)
產(chǎn)品目錄頁(yè)面: 655 (CN2011-ZH PDF)
SC16C850
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 11 November 2010
31 of 55
NXP Semiconductors
SC16C850
2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
7.9 Extra Feature Control Register (EFCR)
This is a write-only register, and it allows the software access to these registers: ‘first extra
feature register set’, ‘second extra feature register set’, Transmit FIFO Level Counter
(TXLVLCNT), and Receive FIFO Level Counter (RXLVLCNT).
Remark: EFCR[2:1] has higher priority than EFCR[0]. TXLVLCNT and RXLVLCNT can
only be accessed if EFCR[2:1] are zeroes.
7.10 Scratchpad Register (SPR)
The SC16C850 provides a temporary data register to store 8 bits of user information.
7.11 Divisor Latch (DLL and DLM)
These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock
in the baud rate generator. DLM, stores the most significant part of the divisor. DLL stores
the least significant part of the divisor.
7.12 Transmit FIFO Level Count (TXLVLCNT)
This register is a read-only register. It reports the number of spaces available in the
transmit FIFO.
7.13 Receive FIFO Level Count (RXLVLCNT)
This register is a read-only register. It reports the fill level of the receive FIFO (the number
of characters in the RX FIFO).
Table 22.
Extra Feature Control Register bits description
Bit
Symbol
Description
7:3
EFCR[7:3]
reserved
2:1
EFCR[2:1]
Enable Extra Feature Control bits
00 = General register set is accessible
01 = First extra feature register set is accessible
10 = Second extra feature register set is accessible
11 = reserved
0
EFCR[0]
Enable TXLVLCNT and RXLVLCNT access
0 = TXLVLCNT and RXLVLCNT are disabled
1 = TXLVLCNT and RXLVLCNT are enabled and can be read.
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PIC16F1827T-I/SO 功能描述:8位微控制器 -MCU 7KB Flash 384 byte 32 MHz Int. Osc RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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