
2012 Microchip Technology Inc.
Preliminary
DS41624B-page 27
PIC16(L)F1512/3
Bank 2
10Ch LATA
PORTA Data Latch
xxxx xxxx uuuu uuuu
10Dh LATB
PORTB Data Latch
xxxx xxxx uuuu uuuu
10Eh LATC
PORTC Data Latch
xxxx xxxx uuuu uuuu
10Fh
to
115h
—
Unimplemented
—
116h BORCON
SBOREN
BORFS
—
BORRDY 10-- ---q uu-- ---u
117h FVRCON
FVREN
FVRRDY
TSEN
TSRNG
—
—ADFVR<1:0>
0q00 --00 0q00 --00
118h
to
11Ch
—
Unimplemented
—
11Dh APFCON
—
SSSEL
CCP2SEL ---- --00 ---- --00
11Eh —
Unimplemented
—
11Fh —
Unimplemented
—
Bank 3
18Ch ANSELA
—
—ANSA5
—
ANSA3
ANSA2
ANSA1
ANSA0
--1- 1111 --1- 1111
18Dh ANSELB
—
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
--11 1111 --11 1111
18Eh ANSELC
ANSC7
ANSC6
ANSC5
ANSC4
ANSC3
ANSC2
—
1111 1100 1111 1100
18Fh —
Unimplemented
—
190h —
Unimplemented
—
191h PMADRL
Program Memory Address Register Low Byte
0000 0000 0000 0000
192h PMADRH
—
Program Memory Address Register High Byte
1000 0000 1000 0000
193h PMDATL
Program Memory Data Register Low Byte
xxxx xxxx uuuu uuuu
194h PMDATH
—
Program Memory Data Register High Byte
--xx xxxx --uu uuuu
195h PMCON1
—(2)
CFGS
LWLO
FREE
WRERR
WREN
WR
RD
1000 x000 1000 q000
196h PMCON2
Program Memory Control Register 2
0000 0000 0000 0000
197h VREGCON(1)
—
VREGPM Reserved ---- --01 ---- --01
198h —
Unimplemented
—
199h RCREG
USART Receive Data Register
0000 0000 0000 0000
19Ah TXREG
USART Transmit Data Register
0000 0000 0000 0000
19Bh SPBRGL
BRG<7:0>
0000 0000 0000 0000
19Ch SPBRGH
BRG<15:8>
0000 0000 0000 0000
19Dh RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x 0000 000x
19Eh TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
0000 0010 0000 0010
19Fh BAUDCON
ABDOVF
RCIDL
—
SCKP
BRG16
—
WUE
ABDEN
01-0 0-00 01-0 0-00
TABLE 3-9:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Legend:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note
1:
PIC16F1512/3 only.
2:
Unimplemented, read as ‘1’.
3:
This register is available in Bank 1 and Bank 14 under similar register names. See Section 16.5.1 “ADC Register Mapping”.