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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� PIC16F1513-E/SS
寤犲晢锛� Microchip Technology
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鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MCU 8BIT 7KB FLASH 28-SSOP
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绯诲垪锛� PIC® XLP™ 16F
鏍稿績铏曠悊鍣細 PIC
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绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
RAM 瀹归噺锛� 256 x 8
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鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 17x10b
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PIC16(L)F1512/3
DS41624B-page 220
Preliminary
2012 Microchip Technology Inc.
20.6.7
I2C MASTER MODE RECEPTION
Master mode reception is enabled by programming the
Receive Enable bit, RCEN bit of the SSPCON2
register.
The Baud Rate Generator begins counting and on each
rollover, the state of the SCL pin changes
(high-to-low/low-to-high) and data is shifted into the
SSPSR. After the falling edge of the eighth clock, the
receive enable flag is automatically cleared, the
contents of the SSPSR are loaded into the SSPBUF,
the BF flag bit is set, the SSPIF flag bit is set and the
Baud Rate Generator is suspended from counting,
holding SCL low. The MSSP is now in Idle state
awaiting the next command. When the buffer is read by
the CPU, the BF flag bit is automatically cleared. The
user can then send an Acknowledge bit at the end of
reception by setting the Acknowledge Sequence
Enable, ACKEN bit of the SSPCON2 register.
20.6.7.1
BF Status Flag
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
20.6.7.2
SSPOV Status Flag
In receive operation, the SSPOV bit is set when eight
bits are received into the SSPSR and the BF flag bit is
already set from a previous reception.
20.6.7.3
WCOL Status Flag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write does not occur).
20.6.7.4
Typical Receive Sequence:
1.
The user generates a Start condition by setting
the SEN bit of the SSPCON2 register.
2.
SSPIF is set by hardware on completion of the
Start.
3.
SSPIF is cleared by software.
4.
User writes SSPBUF with the slave address to
transmit and the R/W bit set.
5.
Address is shifted out the SDA pin until all eight
bits are transmitted. Transmission begins as
soon as SSPBUF is written to.
6.
The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit of the SSPCON2 register.
7.
The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
8.
User sets the RCEN bit of the SSPCON2 register
and the master clocks in a byte from the slave.
9.
After the 8th falling edge of SCL, SSPIF and BF
are set.
10. Master clears SSPIF and reads the received
byte from SSPUF, clears BF.
11. Master sets ACK value sent to slave in ACKDT
bit of the SSPCON2 register and initiates the
ACK by setting the ACKEN bit.
12. Masters ACK is clocked out to the slave and
SSPIF is set.
13. User clears SSPIF.
14. Steps 8-13 are repeated for each received byte
from the slave.
15. Master sends a not ACK or Stop to end
communication.
Note:
The MSSP module must be in an Idle
state before the RCEN bit is set or the
RCEN bit will be disregarded.
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