參數(shù)資料
型號(hào)： PIC16CR77T-I/ML
廠商： Microchip Technology
文件頁數(shù)： 91/172頁
文件大?。?/td> 0K
描述： IC PIC MCU 8KX14 44QFN
標(biāo)準(zhǔn)包裝： 1,600
系列： PIC® 16C
核心處理器： PIC
芯體尺寸： 8-位
速度： 20MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 33
程序存儲(chǔ)器容量： 14KB（8K x 14）
程序存儲(chǔ)器類型： ROM
RAM 容量： 368 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x8b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-VQFN 裸露焊盤
包裝： 帶卷 (TR)
2007 Microchip Technology Inc.
DS21993C-page 23
PIC16CR7X
2.2.2.5
PIR1 Register
The PIR1 register contains the individual flag bits for
the peripheral interrupts.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate interrupt
bits are clear prior to enabling an interrupt.
REGISTER 2-5:
PIR1: (ADDRESS 0Ch)
R/W-0
R-0
R/W-0
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit
1
= A read or a write operation has taken place (must be cleared in software)
0
= No read or write has occurred
bit 6
ADIF: A/D Converter Interrupt Flag bit
1
= An A/D conversion is completed (must be cleared in software)
0
= The A/D conversion is not complete
bit 5
RCIF: USART Receive Interrupt Flag bit
1
= The USART receive buffer is full
0
= The USART receive buffer is empty
bit 4
TXIF: USART Transmit Interrupt Flag bit
1
= The USART transmit buffer is empty
0
= The USART transmit buffer is full
bit 3
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag
1
= The SSP interrupt condition has occurred, and must be cleared in software before
returning from the Interrupt Service Routine. The conditions that will set this bit are:
SPI
A transmission/reception has taken place.
I2C Slave
A transmission/reception has taken place.
I2C Master
A transmission/reception has taken place.
The initiated Start condition was completed by the SSP module.
The initiated Stop condition was completed by the SSP module.
The initiated Restart condition was completed by the SSP module.
The initiated Acknowledge condition was completed by the SSP module.
A Start condition occurred while the SSP module was Idle (multi-master system).
A Stop condition occurred while the SSP module was Idle (multi-master system).
0
= No SSP interrupt condition has occurred
bit 2
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1
= A TMR1 register capture occurred (must be cleared in software)
0
= No TMR1 register capture occurred
Compare mode:
1
= A TMR1 register compare match occurred (must be cleared in software)
0
= No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 1
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1
= TMR2 to PR2 match occurred (must be cleared in software)
0
= No TMR2 to PR2 match occurred
bit 0
TMR1IF: TMR1 Overflow Interrupt Flag bit
1
= TMR1 register overflowed (must be cleared in software)
0
= TMR1 register did not overflow
Note
1:
PSPIF is reserved on 28-pin devices; always maintain this bit clear.
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