參數(shù)資料
型號： PIC16CR77T-I/ML
廠商： Microchip Technology
文件頁數(shù)： 70/172頁
文件大小： 0K
描述： IC PIC MCU 8KX14 44QFN
標準包裝： 1,600
系列： PIC® 16C
核心處理器： PIC
芯體尺寸： 8-位
速度： 20MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 33
程序存儲器容量： 14KB（8K x 14）
程序存儲器類型： ROM
RAM 容量： 368 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x8b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-VQFN 裸露焊盤
包裝： 帶卷 (TR)
2007 Microchip Technology Inc.
DS39599G-page 159
PIC18F2220/2320/4220/4320
17.3.3
ENABLING SPI I/O
To enable the serial port, MSSP Enable bit, SSPEN
(SSPCON1<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, re-initialize the
SSPCON registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pins. For the pins to behave as the serial port func-
tion, some must have their data direction bits (in the
TRIS register) appropriately programmed. That is:
SDI must have TRISC<4> bit cleared
SDO must have TRISC<5> bit cleared
SCK (Master mode) must have TRISC<3> bit
cleared
SCK (Slave mode) must have TRISC<3> bit set
SS must have TRISA<5> bit set
Any serial port function that is not desired may be over-
ridden by programming the corresponding data
direction (TRIS) register to the opposite value.
17.3.4
TYPICAL CONNECTION
Register 17-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge and latched on the opposite edge
of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
Master sends data – Slave sends dummy data
Master sends data – Slave sends data
Master sends dummy data – Slave sends data
FIGURE 17-2:
SPI MASTER/SLAVE CONNECTION
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
MSb
LSb
SDO
SDI
PROCESSOR 1
SCK
SPI Master SSPM3:SSPM0 = 00xxb
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
LSb
MSb
SDI
SDO
PROCESSOR 2
SCK
SPI Slave SSPM3:SSPM0 = 010xb
Serial Clock
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