
PIC16C7X
DS30390B-page 130
1995 Microchip Technology Inc.
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
Legend:
u
= unchanged,
x
= unknown,
-
= unimplemented bit, read as '0',
q
= value depends on condition
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 14-9 for reset value for specific condition.
0000 0000
0000 0000
uuuu uuuu
-000 0000
-000 0000
-uuu uuuu
xxxx xxxx
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
xxxx xxxx
uuuu uuuu
uuuu uuuu
xxxx xxxx
uuuu uuuu
uuuu uuuu
--00 0000
--00 0000
--uu uuuu
0000 -00x
0000 -00x
uuuu -uuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
xxxx xxxx
uuuu uuuu
uuuu uuuu
xxxx xxxx
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
00-0 0000
00-0 0000
uu-u uuuu
0000 00-0
0000 00-0
uuuu uu-u
OPTION
1111 1111
1111 1111
uuuu uuuu
TRISA
---1 1111
---1 1111
---u uuuu
--11 1111
--11 1111
--uu uuuu
TRISB
TRISC
TRISD
TRISE
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
uuuu uuuu
0000 -111
0000 -111
uuuu -uuu
PIE1
-0-- 0000
-0-- 0000
-u-- uuuu
-000 0000
-000 0000
-uuu uuuu
0000 0000
0000 0000
uuuu uuuu
PIE2
---- ---0
---- ---0
---- ---u
PCON
---- --0-
---- --u-
---- --u-
---- --0u
---- --uu
---- --uu
PR2
SSPADD
SSPSTAT
TXSTA
SPBRG
1111 1111
1111 1111
1111 1111
0000 0000
0000 0000
uuuu uuuu
--00 0000
--00 0000
--uu uuuu
0000 -010
0000 -010
uuuu -uuu
0000 0000
0000 0000
uuuu uuuu
ADCON1
---- --00
---- --00
---- --uu
---- -000
---- -000
---- -uuu
TABLE 14-10: INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.’d)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
Wake-up via
WDT or
Interrupt