參數(shù)資料
型號: PIC16C77-10/P
廠商: Microchip Technology
文件頁數(shù): 84/114頁
文件大?。?/td> 0K
描述: IC MCU OTP 8KX14 A/D PWM 40DIP
產(chǎn)品培訓模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝: 10
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 10MHz
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 33
程序存儲器容量: 14KB(8K x 14)
程序存儲器類型: OTP
RAM 容量: 368 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
數(shù)據(jù)轉換器: A/D 8x8b
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 40-DIP(0.600",15.24mm)
包裝: 管件
配用: 444-1001-ND - DEMO BOARD FOR PICMICRO MCU
1997 Microchip Technology Inc.
DS30390E-page 71
PIC16C7X
10.0
CAPTURE/COMPARE/PWM
MODULE(s)
Each CCP (Capture/Compare/PWM) module contains
a 16-bit register which can operate as a 16-bit capture
register, as a 16-bit compare register or as a PWM
master/slave Duty Cycle register. Both the CCP1 and
CCP2 modules are identical in operation, with the
exception of the operation of the special event trigger.
Table 10-1 and Table 10-2 show the resources and
interactions of the CCP module(s). In the following sec-
tions, the operation of a CCP module is described with
respect to CCP1. CCP2 operates the same as CCP1,
except where noted.
Applicable Devices
72 73 73A 74 74A 76 77 CCP1
72 73 73A 74 74A 76 77 CCP2
CCP1 module:
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
CCP2 module:
Capture/Compare/PWM Register2 (CCPR2) is com-
prised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. All are readable and writable.
For use of the CCP modules, refer to the Embedded
Control Handbook,
"Using the CCP Modules" (AN594).
TABLE 10-1:
CCP MODE - TIMER
RESOURCE
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1
Timer2
TABLE 10-2:
INTERACTION OF TWO CCP MODULES
CCPx Mode CCPy Mode
Interaction
Capture
Same TMR1 time-base.
Capture
Compare
The compare should be congured for the special event trigger, which clears TMR1.
Compare
The compare(s) should be congured for the special event trigger, which clears TMR1.
PWM
The PWMs will have the same frequency, and update rate (TMR2 interrupt).
PWM
Capture
None
PWM
Compare
None
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