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| 型號(hào)： | PIC16C74 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 8-Bit CMOS Microcontroller with A/D Converter(每個(gè)I/O口有25mA驅(qū)動(dòng)/吸收電流,1路捕捉/比較/PWM的微控制器) |
| 中文描述： | 8位CMOS微控制器與A / D轉(zhuǎn)換器（每個(gè)的I / O口有25毫安驅(qū)動(dòng)/吸收電流，1路捕捉/比較/脈寬調(diào)制的微控制器） |
| 文件頁(yè)數(shù)： | 83/308頁(yè) |
| 文件大小： | 2351K |
| 代理商： | PIC16C74 |
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1995 Microchip Technology Inc.
DS30390B-page 83
PIC16C7X
11.2
I
Applicable Devices
70 71 71A 72 73 73A 74 74A
2
C
Overview
This section provides an overview of the Inter-Inte-
grated Circuit (I
C) bus, with Section 11.3 discussing
the operation of the SSP module in I
The I
C bus is a two-wire serial interface developed by
the Philips Corporation. The original specification, or
standard mode, was for data transfers of up to 100
Kbps. An enhanced specification, or fast mode, sup-
ports data transmission up to 400 Kbps. Both standard
mode and fast mode devices will inter-operate if
attached to the same bus.
The I
ensure reliable transmission and reception of data.
When transmitting data, one device is the “master”
(generates the clock), while the other device(s) acts as
the “slave.” All portions of the slave protocol are imple-
mented in the SSP module’s hardware, while portions
of the master protocol need to be addressed in the
PIC16CXX software. Table 11-2 defines some of the
I
2
C bus terminology. For additional information on the
I
2
C interface specification, refer to the Philips docu-
ment “The I
2
C bus and how to use it.” which can be
obtained from the Philips Corporation.
In the I
2
C interface protocol each device has an
address. When a master wishes to initiate a data trans-
fer, it first transmits the address of the device that it
wishes to “talk” to. All devices “l(fā)isten” to see if this is
their address. Within this address, a bit specifies if the
master wishes to read-from/write-to the slave device.
The master and slave are always in opposite modes
(transmitter/receiver) of operation during a data trans-
fer. That is they can be thought of operating in either of
these two relations:
Master-transmitter and Slave-receiver
Slave-transmitter and Master-receiver
In both cases the master generates the clock signal.
2
2
C mode.
2
2
C interface employs a comprehensive protocol to
The output stages of the clock (SCL) and data (SDA)
lines must have an open-drain or open-collector in
order to perform the wired-AND function of the bus.
External pull-up resistors are used to ensure a high
level when no device is pulling the line down. The num-
ber of devices that may be attached to the I
2
C bus is
limited only by the maximum bus loading specification
of 400 pF.
11.2.1
INITIATING AND TERMINATING DATA
TRANSFER
During times of no data transfer (idle time), both the
clock line (SCL) and the data line (SDA) are pulled high
through the external pull-up resistors. The START and
STOP conditions determine the start and stop of data
transmission. The START condition is defined as a high
to low transition of the SDA when the SCL is high. The
STOP condition is defined as a low to high transition of
the SDA when the SCL is high. Figure 11-7 shows the
START and STOP conditions. The master generates
these conditions for starting and terminating data trans-
fer. Due to the definition of the START and STOP con-
ditions, when data is being transmitted, the SDA line
can only change state when the SCL line is low.
FIGURE 11-7: START AND STOP
CONDITIONS
SDA
SCL
S
P
Start
Condition
Change
of Data
Allowed
Change
of Data
Allowed
Stop
Condition
TABLE 11-2:
I
2
C BUS TERMINOLOGY
Term
Description
Transmitter
The device that sends the data to the bus.
Receiver
The device that receives the data from the bus.
Master
The device which initiates the transfer, generates the clock and terminates the transfer.
Slave
The device addressed by a master.
Multi-master
More than one master device in a system. These masters can attempt to control the bus at the
same time without corrupting the message.
Arbitration
Procedure that ensures that only one of the master devices will control the bus. This ensure that
the transfer data does not get corrupted.
Synchronization
Procedure where the clock signals of two or more devices are synchronized.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PIC16C74-04/L | 制造商:Microchip Technology Inc 功能描述: |
| PIC16C74-04/P | 制造商:Microchip Technology Inc 功能描述: 制造商:Microchip Technology Inc 功能描述:MicroController, 8-Bit, 40 Pin, Plastic, DIP |
| PIC16C74-10/PQ | 制造商:Microchip Technology Inc 功能描述: |
| PIC16C745/JW | 功能描述:8位微控制器 -MCU 14KB 256 RAM 22 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC16C745-I/SO | 功能描述:8位微控制器 -MCU 14KB 256 RAM 22 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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