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PIC16C7X
DS30390B-page 138
1995 Microchip Technology Inc.
14.8
Power-down Mode (SLEEP)
Applicable Devices
70 71 71A 72 73 73A 74 74A
Power-down mode is entered by executing a
SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (STATUS<3>) is cleared, the
TO (STATUS<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before the
SLEEP
instruction was executed (driving
high, low, or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either V
DD
, or V
SS
, ensure no external cir-
cuitry is drawing current from the I/O pin, power-down
the A/D, disable external clocks. Pull all I/O pins, that
are hi-impedance inputs, high or low externally to avoid
switching currents caused by floating inputs. The
T0CKI input should also be at V
DD
or V
SS
for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (V
IHMC
).
14.8.1
WAKE-UP FROM SLEEP
The device can wake up from SLEEP through one of
the following events:
1.
External reset input on MCLR pin.
2.
Watchdog Timer Wake-up (if WDT was
enabled).
3.
Interrupt from INT pin, RB port change, or some
Peripheral Interrupts.
External MCLR Reset will cause a device reset. All
other events are considered a continuation of program
execution and cause a "wake-up". The TO and PD bits
in the STATUS register can be used to determine the
cause of device reset. The PD bit, which is set on
power-up is cleared when
SLEEP
is invoked. The TO bit
is cleared if WDT time-out occurred (and caused wake-
up).
The following peripheral interrupts can wake the device
from SLEEP:
1.
TMR1 interrupt. Timer1 must be operating as
an asynchronous counter.
2.
SSP (Start/Stop) bit detect interrupt.
3.
SSP transmit or receive in slave mode (SPI/
I
2
C).
4.
CCP capture mode interrupt.
5.
Parallel Slave Port read or write.
6.
A/D conversion (when A/D clock source is RC).
7.
Special event trigger (Timer1 in asynchronous
mode using an external clock).
8.
USART TX or RX (synchronous slave mode).
Other peripherals can not generate interrupts since
during SLEEP, no on-chip Q clocks are present.
When the
SLEEP
instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the
SLEEP
instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the
SLEEP
instruction and then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following
SLEEP
is not desirable, the
user should have a
NOP
after the
SLEEP
instruction.
The WDT is cleared when the device wakes-up from
sleep, regardless of the source of wake-up.
Note:
Interrupts that are capable of waking the
device from SLEEP will still set the individ-
ual flag bits regardless of the state of the
global enable bit, GIE.
FIGURE 14-25: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1
Q2
Q3 Q4
Q1 Q2
Q3
Q4
Q1
Q1
Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1
Q2 Q3
Q4
Q1 Q2
Q3
Q4
OSC1
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
fetched
Instruction
executed
PC
PC+1
PC+2
Inst(PC) = SLEEP
Inst(PC - 1)
Inst(PC + 1)
SLEEP
Processor in
SLEEP
Interrupt Latency
(Note 2)
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h)
Inst(0005h)
Inst(0004h)
Dummy cycle
PC + 2
0004h
0005h
Dummy cycle
T
OST
(2)
PC+2
Note
1:
2:
3:
4:
XT, HS or LP oscillator mode assumed.
T
OST
= 1024T
OSC
(drawing not to scale) This delay will not be there for RC osc mode.
GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
CLKOUT is not available in these osc modes, but shown here for timing reference.