![](http://datasheet.mmic.net.cn/260000/PIC16LC72_datasheet_15942878/PIC16LC72_118.png)
PIC16C7X
DS30390B-page 118
1995 Microchip Technology Inc.
13.5
A/D Operation During Sleep
Applicable Devices
70 71 71A 72 73 73A 74 74A
The A/D module can operate during SLEEP mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 =
11
). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the
SLEEP
instruction to be executed, which eliminates all digital
switching noise from the conversion. When the conver-
sion is completed the GO/DONE bit will be cleared, and
the result loaded into the ADRES register. If the A/D
interrupt is enabled, the device will wake-up from
SLEEP. If the A/D interrupt is not enabled, the A/D mod-
ule will then be turned off, although the ADON bit will
remain set.
When the A/D clock source is another clock option (not
RC), a
SLEEP
instruction will cause the present conver-
sion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
Turning off the A/D places the A/D module in its lowest
current consumption state.
13.6
A/D Accuracy/Error
Applicable Devices
70 71 71A 72 73 73A 74 74A
The overall accuracy of the A/D is less than
±
1 LSb for
V
DD
= 5V
±
10% and the analog V
REF
= V
DD
. This over-
all accuracy includes offset error, full scale error, and
integral error. The A/D converter is guaranteed to be
monotonic. The resolution and accuracy may be less
when either the analog reference (V
DD
) is less than
5.0V or when the analog reference (V
REF
) is less than
V
DD
.
The maximum pin leakage current is
±
5
μ
A.
In systems where the device frequency is low, use of
the A/D RC clock derived from the device oscillator, is
preferred. At moderate to high frequencies, T
AD
should
be derived from the device oscillator. T
AD
must not vio-
late the minimum and should be
≤
8
μ
s for preferred
operation. This is because T
AD
, when derived from
T
OSC
, is kept away from on-chip phase clock transi-
tions. This reduces, to a large extent, the effects of dig-
ital switching noise. This is not possible with the RC
derived clock. The loss of accuracy due to digital
switching noise can be significant if many I/O pins are
active.
Note:
For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS1:ADCS0 =
11
). To perform an A/D
conversion in SLEEP, the GO/DONE bit
must be set, followed by the
SLEEP
instruc-
tion.
In systems where the device will enter SLEEP mode
after the start of the A/D conversion, the RC clock
source selection is required. In this mode, the digital
noise from the modules in SLEEP are stopped. This
method gives high accuracy.
13.7
Effects of a RESET
Applicable Devices
70 71 71A 72 73 73A 74 74A
A device reset forces all registers to their reset state.
This forces the A/D module to be turned off, and any
conversion is aborted. The value that is in the ADRES
register is not modified for a Power-on Reset. The
ADRES register will contain unknown data after a
Power-on Reset.
13.8
Use of the CCP Trigger
Applicable Devices
70 71 71A 72 73 73A 74 74A
An A/D conversion can be started by the “special event
trigger” of the CCP2 module (CCP1 on the PIC16C72
only). This requires that the CCP2M3:CCP2M0 bits
(CCP2CON<3:0>) be programmed as
1011
and that
the A/D module is enabled (ADON bit is set). When the
trigger occurs, the GO/DONE bit will be set, starting the
A/D conversion, and the Timer1 counter will be reset to
zero. Timer1 is reset to automatically repeat the A/D
sampling period with minimal software overhead (mov-
ing the ADRES to the desired location). The appropri-
ate analog input channel must be selected and the
minimum sampling done before the “special event trig-
ger” sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared),
then the “special event trigger” will be ignored by the
A/D module, but will still reset the Timer1 counter.
Note:
In the PIC16C72 the "special event trigger"
is implemented in the CCP1 module.