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| 型號(hào)： | PIC16C62 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 8-Bit CMOS Microcontrollers(每個(gè)I/O口有25mA驅(qū)動(dòng)/吸收電流,22個(gè)I/O,2.5V的微控制器) |
| 中文描述： | 8位CMOS微控制器（每個(gè)的I / O口有25毫安驅(qū)動(dòng)/吸收電流，22個(gè)的I / O，為2.5V的微控制器） |
| 文件頁(yè)數(shù)： | 141/336頁(yè) |
| 文件大?。?/td> | 3529K |
| 代理商： | PIC16C62 |
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1997 Microchip Technology Inc.
DS30234D-page 141
PIC16C6X
13.8
Power-down Mode (SLEEP)
Power-down mode is entered by executing a
SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, status bit PD (STATUS<3>) is cleared,
status bit TO (STATUS<4>) is set, and the oscillator
driver is turned off. The I/O ports maintain the status
they had before the
SLEEP
instruction was executed
(driving high, low, or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either V
DD
, or V
SS
, ensure no external cir-
cuitry is drawing current from the I/O pin, and disable
external clocks. Pull all I/O pins, that are hi-impedance
inputs, high or low externally to avoid switching cur-
rents caused by floating inputs. The T0CKI input should
also be at V
DD
or V
SS
for lowest current consumption.
The contribution from on-chip pull-ups on PORTB
should be considered.
The MCLR/V
PP
pin must be at a logic high level
(V
IHMC
).
13.8.1
WAKE-UP FROM SLEEP
The device can wake from SLEEP through one of the
following events:
1.
External reset input on MCLR/V
PP
pin.
2.
Watchdog Timer Wake-up (if WDT was
enabled).
3.
Interrupt from RB0/INT pin, RB port change, or
some peripheral interrupts.
External MCLR Reset will cause a device reset. All
other events are considered a continuation of program
execution and cause a “wake-up”. The TO and PD bits
in the STATUS register can be used to determine the
cause of device reset. The PD bit, which is set on
power-up is cleared when
SLEEP
is invoked. The TO bit
is cleared if WDT time-out occurred (and caused wake-
up).
The following peripheral interrupts can wake the device
from SLEEP:
1.
TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
2.
SSP (Start/Stop) bit detect interrupt.
3.
SSP transmit or receive in slave mode (SPI/I
2
C).
4.
CCP capture mode interrupt.
5.
Parallel Slave Port read or write.
6.
USART TX or RX (synchronous slave mode).
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
Other peripherals can not generate interrupts since
during SLEEP, no on-chip Q clocks are present.
When the
SLEEP
instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the
SLEEP
instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the
SLEEP
instruction and then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following
SLEEP
is not desirable, the
user should have a
NOP
after the
SLEEP
instruction.
13.8.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
If the interrupt occurs
before
the execution of a
SLEEP
instruction, the
SLEEP
instruction will com-
plete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bits will not be cleared.
If the interrupt occurs
during or after
the execu-
tion of a
SLEEP
instruction, the device will imme-
diately wake up from sleep. The
SLEEP
instruction
will be completely executed before the wake-up.
Therefore, the WDT and WDT postscaler will be
cleared, the TO bit will be set and the PD bit will
be cleared.
Even if the flag bits were checked before executing a
SLEEP
instruction, it may be possible for flag bits to
become set before the
SLEEP
instruction completes. To
determine whether a
SLEEP
instruction executed, test
the PD bit. If the PD bit is set, the
SLEEP
instruction
was executed as a NOP.
To ensure that the WDT is cleared, a
CLRWDT
instruc-
tion should be executed before a
SLEEP
instruction.
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