參數(shù)資料
型號: PIC12F519-I/MS
廠商: Microchip Technology
文件頁數(shù): 51/96頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 1KX12 8MSOP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝: 100
系列: PIC® 12F
核心處理器: PIC
芯體尺寸: 8-位
速度: 8MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 5
程序存儲器容量: 1.5KB(1K x 12)
程序存儲器類型: 閃存
RAM 容量: 41 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 637 (CN2011-ZH PDF)
配用: AC162096-ND - HEADER MPLAB ICD2 PIC16F526 8/14
AC164325-ND - MODULE SKT FOR 8MSOP
2008 Microchip Technology Inc.
DS41319B-page 53
PIC12F519
DECF
Decrement f
Syntax:
[ label ] DECF f,d
Operands:
0
≤ f ≤ 31
d
∈ [0,1]
Operation:
(f) – 1
→ (dest)
Status Affected: Z
Description:
Decrement register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
DECFSZ
Decrement f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Operands:
0
≤ f ≤ 31
d
∈ [0,1]
Operation:
(f) – 1
→ d; skip if result = 0
Status Affected: None
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘0’, the next instruc-
tion, which is already fetched, is
discarded and a NOP is executed
instead making it a two-cycle
instruction.
GOTO
Unconditional Branch
Syntax:
[ label ]
GOTO k
Operands:
0
≤ k ≤ 511
Operation:
k
→ PC<8:0>;
STATUS<6:5>
→ PC<10:9>
Status Affected: None
Description:
GOTO
is an unconditional branch.
The 9-bit immediate value is
loaded into PC bits <8:0>. The
upper bits of PC are loaded from
STATUS<6:5>. GOTO is a two-
cycle instruction.
INCF
Increment f
Syntax:
[ label ] INCF f,d
Operands:
0
≤ f ≤ 31
d
∈ [0,1]
Operation:
(f) + 1
→ (dest)
Status Affected: Z
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ] INCFSZ f,d
Operands:
0
≤ f ≤ 31
d
∈ [0,1]
Operation:
(f) + 1
→ (dest), skip if result = 0
Status Affected: None
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘0’, then the next
instruction, which is already
fetched, is discarded and a NOP is
executed instead making it a
two-cycle instruction.
IORLW
Inclusive OR literal with W
Syntax:
[ label ] IORLW k
Operands:
0
≤ k ≤ 255
Operation:
(W) .OR. (k)
→ (W)
Status Affected: Z
Description:
The contents of the W register are
OR’ed with the eight-bit literal ‘k’.
The result is placed in the
W register.
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