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參數(shù)資料
| 型號： | PIC12F510-I/MS |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 6/39頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PIC MCU FLASH 1.5KB 8MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 系列： | PIC® 12F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 8MHz |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 5 |
| 程序存儲器容量： | 1.5KB（1K x 12） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 38 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 4x8b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 637 (CN2011-ZH PDF) |
| 配用： | AC162070-ND - HEADER INTRFC MPLAB ICD2 8/14P AC164325-ND - MODULE SKT FOR 8MSOP |
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14
6462AS–ATARM–03-Jun-09
AT91SAM9G10
7.2
Debug and Test Features
Integrated Embedded In-circuit Emulator Real-Time
– Two real-time Watchpoint Units
– Two Independent Registers: Debug Control Register and Debug Status Register
– Test Access Port Accessible through JTAG Protocol
– Debug Communications Channel
Debug Unit
–Two-pin UART
– Debug Communication Channel Interrupt Handling
– Chip ID Register
IEEE1149.1 JTAG Boundary-scan on All Digital Pins
7.3
Bus Matrix
Five Masters and Five Slaves handled
– Handles Requests from the ARM926EJ-S, USB Host Port, LCD Controller and the
Peripheral DMA Controller to internal ROM, internal SRAM, EBI, APB, LCD
Controller and USB Host Port.
– Round-Robin Arbitration (three modes supported: no default master, last accessed
default master, fixed default master)
– Burst Breaking with Slot Cycle Limit
One Address Decoder Provided per Master
– Three different slaves may be assigned to each decoded memory area: one for
internal boot, one for external boot, one after remap.
Boot Mode Select Option
– Non-volatile Boot Memory can be Internal or External.
– Selection is made by BMS pin sampled at reset.
Remap Command
– Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory
– Allows Handling of Dynamic Exception Vectors
7.4
Peripheral DMA Controller
Transfers from/to peripheral to/from any memory space without intervention of the processor.
Next Pointer Support, forbids strong real-time constraints on buffer management.
Nineteen channels
– Two for each USART
– Two for the Debug Unit
– Two for each Serial Synchronous Controller
– Two for each Serial Peripheral Interface
– One for the Multimedia Card Interface
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