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參數(shù)資料
| 型號(hào)： | PIC12F510-I/MS |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 16/39頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PIC MCU FLASH 1.5KB 8MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 系列： | PIC® 12F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 8MHz |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 5 |
| 程序存儲(chǔ)器容量： | 1.5KB（1K x 12） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 38 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 4x8b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 637 (CN2011-ZH PDF) |
| 配用： | AC162070-ND - HEADER INTRFC MPLAB ICD2 8/14P AC164325-ND - MODULE SKT FOR 8MSOP |
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23
6462AS–ATARM–03-Jun-09
AT91SAM9G10
9.10
Advanced Interrupt Controller
Controls the interrupt lines (nIRQ and nFIQ) of an ARM Processor
Thirty-two individually maskable and vectored interrupt sources
– Source 0 is reserved for the Fast Interrupt Input (FIQ)
– Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.)
– Source 2 to Source 31 control up to thirty embedded peripheral interrupts or external
interrupts
– Programmable edge-triggered or level-sensitive internal sources
– Programmable positive/negative edge-triggered or high/low level-sensitive
Four External Sources
8-level Priority Controller
– Drives the normal interrupt of the processor
– Handles priority of the interrupt sources 1 to 31
– Higher priority interrupts can be served during service of lower priority interrupt
Vectoring
– Optimizes Interrupt Service Routine Branch and Execution
– One 32-bit Vector Register per interrupt source
– Interrupt Vector Register reads the corresponding current Interrupt Vector
Protect Mode
– Easy debugging by preventing automatic operations when protect mode is enabled
Fast Forcing
– Permits redirecting any normal interrupt source on the Fast Interrupt of the
processor
General Interrupt Mask
– Provides processor synchronization on events without triggering an interrupt
9.11
Debug Unit
Composed of four functions
–Two-pin UART
– Debug Communication Channel (DCC) support
– Chip ID Registers
– ICE Access Prevention
Two-pin UART
– Implemented features are 100% compatible with the standard Atmel USART
– Independent receiver and transmitter with a common programmable Baud Rate
Generator
– Even, Odd, Mark or Space Parity Generation
– Parity, Framing and Overrun Error Detection
– Automatic Echo, Local Loopback and Remote Loopback Channel Modes
– Support for two PDC channels with connection to receiver and transmitter
Debug Communication Channel Support
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