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參數(shù)資料
| 型號： | PIC12F1840T-I/MF |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 12/122頁 |
| 文件大?。?/td> | 0K |
| 描述： | MCU 7KB FLASH 256B RAM XLP 8DFN |
| 標準包裝： | 3,300 |
| 系列： | PIC® XLP™ 12F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 32MHz |
| 連通性： | I²C，LIN，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 5 |
| 程序存儲器容量： | 7KB（4K x 14） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大小： | 256 x 8 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.3 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 4x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-VDFN 裸露焊盤 |
| 包裝： | 帶卷 (TR) |
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2011 Microchip Technology Inc.
Preliminary
DS41441B-page 109
PIC12(L)F1840
REGISTER 11-5:
EECON1: EEPROM CONTROL 1 REGISTER
R/W-0/0
R/W/HC-0/0
R/W-x/q
R/W-0/0
R/S/HC-0/0
EEPGD
CFGS
LWLO
FREE
WRERR
WREN
WR
RD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
S = Bit can only be set
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HC = Bit is cleared by hardware
bit 7
EEPGD:
Flash Program/Data EEPROM Memory Select bit
1
= Accesses program space Flash memory
0
= Accesses data EEPROM memory
bit 6
CFGS:
Flash Program/Data EEPROM or Configuration Select bit
1
= Accesses Configuration, User ID and Device ID Registers
0
= Accesses Flash Program or data EEPROM Memory
bit 5
LWLO:
Load Write Latches Only bit
If CFGS = 1 (Configuration space) OR CFGS = 0 and EEPGD = 1 (program Flash):
1
= The next WR command does not initiate a write; only the program memory latches are
updated.
0
= The next WR command writes a value from EEDATH:EEDATL into program memory latches
and initiates a write of all the data stored in the program memory latches.
If CFGS = 0 and EEPGD = 0: (Accessing data EEPROM)
LWLO is ignored. The next WR command initiates a write to the data EEPROM.
bit 4
FREE:
Program Flash Erase Enable bit
If CFGS = 1 (Configuration space) OR CFGS = 0 and EEPGD = 1 (program Flash):
1
= Performs an erase operation on the next WR command (cleared by hardware after comple-
tion of erase).
0
= Performs a write operation on the next WR command.
If EEPGD = 0 and CFGS = 0: (Accessing data EEPROM)
FREE is ignored. The next WR command will initiate both a erase cycle and a write cycle.
bit 3
WRERR:
EEPROM Error Flag bit
1
= Condition indicates an improper program or erase sequence attempt or termination (bit is set
automatically on any set attempt (write ‘1’) of the WR bit).
0
= The program or erase operation completed normally.
bit 2
WREN:
Program/Erase Enable bit
1
= Allows program/erase cycles
0
= Inhibits programming/erasing of program Flash and data EEPROM
bit 1
WR:
Write Control bit
1
= Initiates a program Flash or data EEPROM program/erase operation.
The operation is self-timed and the bit is cleared by hardware once operation is complete.
The WR bit can only be set (not cleared) in software.
0
= Program/erase operation to the Flash or data EEPROM is complete and inactive.
bit 0
RD:
Read Control bit
1
= Initiates a program Flash or data EEPROM read. Read takes one cycle. RD is cleared in
hardware. The RD bit can only be set (not cleared) in software.
0
= Does not initiate a program Flash or data EEPROM data read.
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