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參數(shù)資料
| 型號： | PIC12C509A-04I/SN |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 25/113頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU OTP 1KX12 8SOIC |
| 產(chǎn)品培訓模塊： | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 標準包裝： | 100 |
| 系列： | PIC® 12C |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 4MHz |
| 外圍設備： | POR，WDT |
| 輸入/輸出數(shù)： | 5 |
| 程序存儲器容量： | 1.5KB（1K x 12） |
| 程序存儲器類型： | OTP |
| RAM 容量： | 41 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 包裝： | 管件 |
| 配用： | ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING 309-1046-ND - ADAPTER 8-SOIC TO 8-DIP 309-1045-ND - ADAPTER 8-SOIC TO 8-DIP |
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1999 Microchip Technology Inc.
DS40139E-page 19
PIC12C5XX
4.6
Program Counter
As a program instruction is executed, the Program
Counter (PC) will contain the address of the next
program instruction to be executed. The PC value is
increased by one every instruction cycle, unless an
instruction changes the PC.
For a GOTO instruction, bits 8:0 of the PC are provided
by the GOTO instruction word. The PC Latch (PCL) is
mapped to PC<7:0>. Bit 5 of the STATUS register
provides page information to bit 9 of the PC (Figure 4-
8).
For a CALL instruction, or any instruction where the
PCL is the destination, bits 7:0 of the PC again are
provided by the instruction word. However, PC<8>
does not come from the instruction word, but is always
cleared (Figure 4-8).
Instructions where the PCL is the destination, or
Modify PCL instructions, include MOVWF PC, ADDWF
PC,
and BSF PC,5.
FIGURE 4-8:
LOADING OF PC
BRANCH INSTRUCTIONS -
PIC12C5XX
Note:
Because PC<8> is cleared in the CALL
instruction, or any Modify PCL instruction,
all subroutine calls or computed jumps are
limited to the first 256 locations of any pro-
gram memory page (512 words long).
PA0
STATUS
PC
87
0
PCL
9
10
Instruction Word
70
GOTO
Instruction
CALL
or Modify PCL Instruction
11
PA0
STATUS
PC
87
0
PCL
9
10
Instruction Word
70
11
Reset to ‘0’
4.6.1
EFFECTS OF RESET
The Program Counter is set upon a RESET, which
means that the PC addresses the last location in the
executing MOVLW XX, the PC will roll over to location
00h, and begin executing user code.
The STATUS register page preselect bits are cleared
upon a RESET, which means that page 0 is pre-
selected.
Therefore, upon a RESET, a
GOTO
instruction will
automatically cause the program to jump to page 0
until the value of the page bits is altered.
4.7
Stack
PIC12C5XX devices have a 12-bit wide L.I.F.O.
hardware push/pop stack.
A CALL instruction will
push the current value of stack
1 into stack 2 and then push the current program
counter value, incremented by one, into stack level 1. If
more than two sequential CALL’s are executed, only
the most recent two return addresses are stored.
A RETLW instruction will
pop the contents of stack level
1 into the program counter and then copy stack level 2
contents into level 1. If more than two sequential
RETLW
’s are executed, the stack will be filled with the
address previously stored in level 2. Note that the
W register will be loaded with the literal value specified
in the instruction. This is particularly useful for the
implementation of data look-up tables within the
program memory.
Upon any reset, the contents of the stack remain
unchanged, however the program counter (PCL) will
also be reset to 0.
Note 1: There are no STATUS bits to indicate
stack overflows or stack underflow condi-
tions.
Note 2: There are no instructions mnemonics
called PUSH or POP. These are actions
that occur from the execution of the CALL
and RETLW instructions.
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相關代理商/技術參數(shù) |
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