參數(shù)資料
型號(hào)： PIC10F206-E/MC
廠商： Microchip Technology
文件頁(yè)數(shù)： 69/94頁(yè)
文件大?。?/td> 0K
描述： IC PIC MCU FLASH 512X12 8DFN
標(biāo)準(zhǔn)包裝： 150
系列： PIC® 10F
核心處理器： PIC
芯體尺寸： 8-位
速度： 4MHz
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 3
程序存儲(chǔ)器容量： 768B（512 x 12）
程序存儲(chǔ)器類(lèi)型： 閃存
RAM 容量： 24 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 8-VFDFN 裸露焊盤(pán)
包裝： 管件
配用： AC164334-ND - MODULE SOCKET FOR 8L 2X3MM DFN
AC163020-2-ND - ADAPTER PROGRAM PIC10F 2X3 DFN
72
AT89/83EB5114
4311C–8051–02/08
Flash Memory
As shown Figure 32, the Flash version of AT8xEB5114 implements 4 Kbytes of on-chip
program/code memory.
The Flash memory increases EPROM and ROM functionality by in-circuit electrical era-
sure and programming. Thanks to the internal charge pump, the high voltage needed for
programming or erasing Flash cells is generated on-chip using the standard VDD
voltage.
Hardware programming mode is available using specific programming tool.
AT8xEB5114 features a Flash memory containing 4 Kbytes of program memory (user
space) organized into 128 byte pages,
This Flash memory is programmable by parallel programming.
Figure 32. Flash Memory Architecture
FM0 Memory
Architecture
The Flash memory is made up of 4 blocks (see Figure 32):
–
The memory array (user space) 4 Kbytes
–
The Extra Row
–
The Hardware security bits
–
The column latch registers
User Space
This space is composed of a 4 Kbytes Flash memory organized in 32 pages of 128
bytes. It contains the user’s application code.
Extra Row (XRow)
This row is a part of flash memory and has a size of 128 bytes. The extra row may con-
tain information for boot loader usage.
Hardware security Byte
The Hardware Security Byte space is a part of flash memory and has a size of 1 byte.
The 4 MSB can be read/written by software, the 4 LSB can only be read by software and
written by hardware in parallel mode.
Column latches
The column latches, also part of flash memory, have a size of full page (128 bytes).
The column latches are the entrance buffers of the three previous memory locations
(user array, XROW and Hardware security byte).
Overview of Flash Memory
Operations
The CPU interfaces to the Flash memory through the FCON register used to:
–
Map the memory spaces in the adressable space
0FFFh
4 Kbytes
Flash memory
0000h
Hardware Security (1 byte)
Column Latches (128 bytes)
user space
Extra Row (128 bytes)
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